Agilent ATF-521P8 High Linearity
Enhancement Mode
[1]
Pseudomorphic HEMT in
2x2 mm
2
LPCC
[3]
Package
Data Sheet
Features
• Single voltage operation
• High linearity and P1dB
Description
Agilent Technologies’s ATF-521P8 is a
single-voltage high linearity, low noise
E-pHEMT housed in an 8-lead JEDEC-
standard leadless plastic chip carrier
(LPCC
[3]
) package. The device is ideal
as a medium-power, high-linearity am-
plifier. Its operating frequency range
is from 50 MHz to 6 GHz.
The thermally efficient package mea-
sures only 2mm x 2mm x 0.75mm. Its
backside metalization provides excel-
lent thermal dissipation as well as vi-
sual evidence of solder reflow. The
device has a Point MTTF of over 300
years at a mounting temperature of
+85°C. All devices are 100% RF & DC
tested.
Pin Connections and
Package Marking
Pin 8
Pin 7 (Drain)
Pin 6
Pin 5
• Low noise figure
• Excellent uniformity in product
specifications
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Source
(Thermal/RF Gnd)
• Small package size:
2.0 x 2.0 x 0.75 mm
3
• Point MTTF > 300 years
[2]
• MSL-1 and lead-free
• Tape-and-reel packaging option
available
Bottom View
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Pin 8
2Px
Top View
Pin 7 (Drain)
Pin 6
Pin 5
Specifications
2 GHz; 4.5V, 200 mA (Typ.)
• 42 dBm output IP3
• 26.5 dBm output power at 1 dB gain
compression
• 1.5 dB noise figure
• 17 dB Gain
Note:
Package marking provides orientation and
identification
“2P” = Device Code
“x” = Month code indicates the month of
manufacture.
Note:
1. Enhancement mode technology employs a
single positive V
gs
, eliminating the need of
negative gate voltage associated with
conventional depletion mode devices.
2. Refer to reliability datasheet for detailed
MTTF data
3. Conform to JEDEC reference outline MO229
for DRP-N
4. Linearity Figure of Merit (LFOM) is essentially
OIP3 divided by DC bias power.
• 12.5 dB LFOM
[4]
Applications
• Front-end LNA Q2 and Q3, driver or
pre-driver amplifier for Cellular/
PCS and WCDMA wireless
infrastructure
• Driver amplifier for WLAN,
WLL/RLL and MMDS applications
• General purpose discrete E-pHEMT
for other high linearity applications
ATF-521P8 Absolute Maximum Ratings
[1]
Symbol
V
DS
V
GS
V
GD
I
DS
I
GS
P
diss
P
in max.
T
CH
T
STG
θ
ch_b
Parameter
Drain – Source Voltage
[2]
Gate – Source Voltage
[2]
Gate Drain Voltage
[2]
Drain Current
[2]
Gate Current
Total Power Dissipation
[3]
RF Input Power
Channel Temperature
Storage Temperature
Thermal Resistance
[4]
Units
V
V
V
mA
mA
W
dBm
°C
°C
°C/W
Absolute
Maximum
7
-5 to 1
-5 to 1
500
46
1.5
27
150
-65 to 150
45
Notes:
1. Operation of this device in excess of any one
of these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. Board (package belly) temperatureT
B
is 25°C.
Derate 22 mW/°C for T
B
> 83°C.
4. Channel to board thermal resistance
measured using 150°C Liquid Crystal
Measurement method.
5. Device can safely handle +27dBm RF Input
Power provided IGS is limited to 46mA. IGS
at P1dB drive level is bias circuit dependent.
Product Consistency Distribution Charts
[5, 6]
600
500
400
I
DS
(mA)
0.8V
0.7V
180
Stdev = 0.19
150
120
90
Vgs = 0.6V
150
Cpk = 0.86
Stdev = 1.32
120
-3 Std
+3 Std
90
-3 Std
+3 Std
300
200
100
0
60
60
30
0
6
8
30
0.5V
0.4V
0
0
0.5
1
1.5
NF (dB)
2
2.5
3
37
39
0
2
4
V
DS
(V)
41
43
OIP3 (dBm)
45
47
49
Figure 1. Typical I-V Curves.
(V
GS
= 0.1 V per step)
Figure 2. NF @ 2 GHz, 4.5 V, 200 mA.
Nominal = 1.5 dB.
Figure 3. OIP3 @ 2 GHz, 4.5 V, 200 mA.
Nominal = 41.9 dBm, LSL = 38.5 dBm.
180
150
120
90
60
30
0
-3 Std
+3 Std
Cpk = 2.13
Stdev = 0.21
300
250
200
150
100
50
0
-3 Std
+3 Std
Cpk = 4.6
Stdev = 0.11
15
16
17
GAIN (dB)
18
19
25
25.5
26
26.5
27
27.5
P1dB (dBm)
Figure 4. Gain @ 2 GHz, 4.5 V, 200 mA.
Nominal = 17.2 dB, LSL = 15.5 dB,
USL = 18.5 dB.
Figure 5. P1dB @ 2 GHz, 4.5 V, 200 mA.
Nominal = 26.5 dBm, LSL = 25 dBm.
Notes:
5. Distribution data sample size is 500 samples taken from 5 different wafers. Future wafers allocated
to this product may have nominal values anywhere between the upper and lower limits.
6. Measurements are made on production test board, which represents a trade-off between optimal
OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.
2
ATF-521P8 Electrical Specifications
T
A
= 25°C, DC bias for RF parameters is Vds = 4.5V and Ids = 200 mA unless otherwise specified.
Symbol
Vgs
Vth
Idss
Gm
Parameter and Test Condition
Operational Gate Voltage
Threshold Voltage
Saturated Drain Current
Transconductance
Vds = 4.5V, Ids = 200 mA
Vds = 4.5V, Ids = 16 mA
Vds = 4.5V, Vgs = 0V
Vds = 4.5V, Gm =
∆Idss/∆Vgs;
Vgs = Vgs1 - Vgs2
Vgs1 = 0.55V, Vgs2 = 0.5V
Vds = 0V, Vgs = -4V
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
Offset BW = 5 MHz
Offset BW = 10 MHz
Units
V
V
µA
mmho
Min.
—
—
—
—
Typ.
0.62
0.28
14.8
1300
Max.
—
—
—
—
Igss
NF
G
OIP3
P1dB
PAE
ACLR
Gate Leakage Current
Noise Figure
[1]
Gain
[1]
Output 3
rd
Order
Intercept Point
[1]
Output 1dB
Compressed
[1]
Power Added Efficiency
Adjacent Channel Leakage
Power Ratio
[1,2]
µA
dB
dB
dB
dB
dBm
dBm
dBm
dBm
%
%
dBc
dBc
-20
—
—
15.5
—
38.5
—
25
—
45
—
—
—
0.49
1.5
1.2
17
17.2
42
42.5
26.5
26.5
60
56
-51.4
-61.5
—
—
—
18.5
—
—
—
—
—
—
—
—
—
Notes:
1. Measurements obtained using production test board described in Figure 6.
2. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
– Test Model 1
– Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
– Freq = 2140 MHz
– Pin = -5 dBm
– Chan Integ Bw = 3.84 MHz
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag
= 0.55
Γ_ang
= -166°
(1.1 dB loss)
DUT
Output
Matching Circuit
Γ_mag
= 0.35
Γ_ang
= 168°
(0.9 dB loss)
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a
trade-off between optimal OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.
3
1 pF
3.9 nH
1.5 pF
50 Ohm
.02
λ
12 nH
15 Ohm
2.2
µF
2.2
µF
110 Ohm
.03
λ
110 Ohm
.03
λ
50 Ohm
.02
λ
1.5 pF
RF Input
DUT
47 nH
RF Output
Gate
Supply
Drain
Supply
Figure 7. Simplified schematic of production test board. Primary purpose is to show 15 Ohm series resistor placement in
gate supply. Transmission line tapers, tee intersections, bias lines and parasitic values are not shown.
Gamma Load and Source at Optimum OIP3 and P1dB Tuning Conditions
The device’s optimum OIP3 and P1dB measurements were determined using a Maury load pull system at
4.5V, 200 mA quiesent bias:
Optimum OIP3
Gamma Load
OIP3
Mag
Ang (deg)
(dBm)
0.314
0.538
0.566
0.495
179.0
-176.0
-169.0
-159.0
42.7
42.5
42.0
40.3
Freq
(GHz)
0.9
2
2.4
3.9
Gamma Source
Mag
Ang (deg)
0.413
0.368
0.318
0.463
10.5
162.0
169.0
-134.0
Gain
(dB)
16.0
15.8
14.1
9.6
P1dB
(dBm)
27.0
27.5
27.4
27.3
PAE
(%)
54.0
55.3
53.5
43.9
Freq
(GHz)
0.9
2
2.4
3.9
Gamma Source
Mag
Ang (deg)
0.587
0.614
0.649
0.552
12.7
126.1
145.0
-162.8
Optimum P1dB
Gamma Load
OIP3
Mag
Ang (deg)
(dBm)
0.613
0.652
0.682
0.670
-172.1
-172.5
-171.5
-151.2
39.1
39.5
40.0
38.1
Gain
(dB)
14.5
12.9
12.0
9.6
P1dB
(dBm)
29.3
29.3
29.4
27.9
PAE
(%)
49.6
49.5
46.8
39.1
4
ATF-521P8 Typical Performance Curves
(at 25°C unless specified otherwise)
Tuned for Optimal OIP3
50
45
40
OIP3 (dBm)
OIP3 (dBm)
35
30
25
20
15
10
100
150
200
250
I
d
(mA)
300
4.5V
4V
3V
45
40
35
OIP3 (dBm)
4.5V
4V
3V
50
45
40
35
30
25
20
15
400
10
100
150
200
250
I
d
(mA)
300
4.5V
4V
3V
30
25
20
15
350
400
10
100
150
200
250
I
d
(mA)
300
350
350
400
Figure 8. OIP3 vs. I
ds
and V
ds
at 2 GHz.
Figure 9. OIP3 vs. I
ds
and V
ds
at 900 MHz.
Figure 10. OIP3 vs. I
ds
and V
ds
at 3.9 GHz.
35
35
35
30
P1dB (dBm)
P1dB (dBm)
30
P1dB (dBm)
4.5V
4V
3V
30
25
25
25
20
4.5V
4V
3V
20
20
4.5V
4V
3V
15
15
15
10
100
150
200
250
I
dq
(mA)
300
350
400
10
100
150
200
250
I
dq
(mA)
300
350
400
10
100
150
200
250
I
dq
(mA)
300
350
400
Figure 11. P1dB vs. I
dq
and V
ds
at 2 GHz.
Figure 12. P1dB vs. I
dq
and V
ds
at 900 MHz.
Figure 13. P1dB vs. I
dq
and V
ds
at 3.9 GHz.
17
16
15
GAIN (dBm)
GAIN (dBm)
14
13
12
11
10
100
4.5V
4V
3V
17
16
15
14
13
12
11
10
100
4.5V
4V
3V
12
11
10
GAIN (dBm)
9
8
7
6
5
100
4.5V
4V
3V
150
200
250
I
d
(mA)
300
350
400
150
200
250
I
d
(mA)
300
350
400
150
200
250
I
d
(mA)
300
350
400
Figure 14. Small Signal Gain vs I
ds
and V
ds
at 2 GHz.
Figure 15. Small Signal Gain vs I
ds
and V
ds
at 900 MHz.
Figure 16. Small Signal Gain vs I
ds
and V
ds
at 3.9 GHz.
Note:
Bias current for the above charts are quiescent
conditions. Actual level may increase depending
on amount of RF drive.
5
Embedded System
京公网安备 11010802033920号
EEWORLD
