2.5V LVDS, 1:6 Clock Buffer Terabuffer
TM
II
IDT8R9306I
DATASHEET
General Description
The IDT8R9306I 2.5V differential clock buffer is a user-selectable
differential input to six LVDS outputs. The fanout from a differential
input to six LVDS outputs reduces loading on the preceding driver
and provides an efficient clock distribution network. The IDT8R9306I
can act as a translator from a differential HSTL, eHSTL, LVPECL
(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A
single-ended 3.3V, 2.5V LVTTL input can also be used to translate to
LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a
secondary clock source. Selectable reference inputs are controlled
by SEL.
The IDT8R9306I outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the GL
pin. Multiple power and grounds reduce noise.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Guaranteed low skew: 40ps (maximum)
Very low duty cycle distortion: <125ps (maximum)
High speed propagation delay: <1.75ns (maximum)
Up to 1GHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL eHSTL, LVPECL (2.5V), LVPECL (3.3V),
CML or LVDS input interface
Selectable differential inputs to six LVDS outputs
Power-down mode
2.5V V
DD
-40°C to 85°C ambient operating temperature
Available in VFQFPN package
Applications
•
Clock distribution
Pin Assignment
nPD
nQ4
21 20 19 18 17 16 15
nc
nQ5
Q5
nQ6
Q6
V
DD
SEL
22
23
24
25
26
27
28
1
nG
2
V
DD
3
Q1
4
nQ1
5
V
DD
6
A1
7
nA1
14
13
12
V
DD
nQ3
Q3
nQ2
Q2
V
DD
GL
nA2
11
10
9
8
V
DD
V
DD
Q4
A2
GND
IDT8R9306I
28-Lead VFQFPN
6mm x 6mm x 0.9mm package body
EPad 4.8mm x 4.8mm
NL Package
Top View
IDT8R9306NLI REVISION D AUGUST 21, 2013
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©2013 Integrated Device Technology, Inc.
IDT8R9306I Data Sheet
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
Block Diagram
GL
nG
OUTPUT
CONTROL
Q1
nQ1
nPD
OUTPUT
CONTROL
Q2
nQ2
A1
nA1
1
OUTPUT
CONTROL
Q3
nQ3
A2
nA2
0
OUTPUT
CONTROL
Q4
nQ4
SEL
OUTPUT
CONTROL
Q5
nQ5
OUTPUT
CONTROL
Q6
nQ6
IDT8R9306NLI REVISION D AUGUST 21, 2013
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©2013 Integrated Device Technology, Inc.
IDT8R9306I Data Sheet
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Name
A[1:2]
Input
Type
Adjustable
(1, 4)
Adjustable
(1, 4)
Description
Clock input. A[1:2] is the "true" side of the differential clock input.
Complementary clock inputs. nA[1:2] is the complementary side of A[1:2]. For LVTTL
single-ended operation, nA[1:2] should be set to the desired toggle voltage for A[1:2]:
3.3V LVTTL V
REF
= 1650mV
2.5V LVTTL V
REF
= 1250mV
Gate control for differential outputs Q[1:6] and nQ[1:6]. When nG is LOW, the differential
outputs are active. When nG is HIGH, the differential outputs are asynchronously driven to
the level designated by GL
(2)
. See Table 3A.
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary"
outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs
disable HIGH. See Table 3A.
Clock outputs.
Complementary clock outputs.
Reference clock select. When LOW, selects A2 and nA2. When HIGH, selects A1 and nA1.
See Table 3B.
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode.
Inputs and outputs are disabled. Both "true" and “complementary” outputs will pull to V
DD
.
Set HIGH for normal operation.
(3)
Power supply for the device core and inputs.
Power supply return for all power.
No connect; recommended to connect to GND.
nA[1:2]
Input
nG
Input
LVTTL
GL
Q[1:6]
nQ[1:6]
SEL
Input
Output
Output
Input
LVTTL
LVDS
LVDS
LVTTL
nPD
V
DD
GND
nc
Input
LVTTL
Power
Power
NOTES:
1
Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2.
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
3.
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting nPD.
4.
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
Table 2. Pin Characteristics,
T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
Maximum
3
Units
pF
NOTE: This parameter is measured at characterization but not tested.
IDT8R9306NLI REVISION D AUGUST 21, 2013
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©2013 Integrated Device Technology, Inc.
IDT8R9306I Data Sheet
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
Function Tables
Table 3A. Gate Control Output Table
Control Output
GL
0
0
1
1
nG
0
1
0
1
Q[1:6]
Toggling
LOW
Toggling
HIGH
Outputs
nQ[1:6]
Toggling
HIGH
Toggling
LOW
Table 3B. Input Selection Table
Selection SEL pin
0
1
Inputs
A2, nA2
A1, nA1
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Power Supply Voltage, V
DD
Input Voltage, V
I
Output Voltage, V
O
Not to exceed 3.6V
Storage Temperature, T
STG
Junction Temperature, T
J
Rating
-0.5V to +3.6V
-0.5V to +3.6V
-0.5 to V
DD
+0.5V
-65C to 150C
150C
Recommended Operating Range
Symbol
T
A
V
DD
Description
Ambient Operating Temperature
Internal Power Supply Voltage
Minimum
-40
2.3
Typical
+25
2.5
Maximum
+85
2.7
Units
C
V
IDT8R9306NLI REVISION D AUGUST 21, 2013
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©2013 Integrated Device Technology, Inc.
IDT8R9306I Data Sheet
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics
(1)
,
T
A
= -40°C to 85°C
Symbol
I
DDQ
I
TOT
I
PD
Parameter
Quiescent V
DD
Power Supply
Current
Total Power V
DD
Supply
Current
Total Power Down Supply
Current
Test Conditions
V
DD
= Max.,
All Input Clocks = LOW
(2)
;
Outputs enabled
V
DD
= 2.7V;
F
REFERENCE
Clock = 1GHz
nPD = LOW
Minimum
Typical
(2)
Maximum
240
Units
mA
250
5
mA
mA
NOTE 1: These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
NOTE 2: The true input is held LOW and the complementary input is held HIGH.
Table 4B. LVCMOS/LVTTL DC Characteristics
(1)
,
T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
IK
V
IN
V
IH
V
IL
V
THI
V
REF
Parameter
Input High Current
Input Low Current
Clamp Diode Voltage
DC Input Voltage
DC Input High Voltage
DC Input Low Voltage
DC Input Threshold Crossing
Voltage
Single-Ended Reference
Voltage
(3)
3.3V LVTTL
2.5V LVTTL
V
DD
/2
1.65
1.25
Test Conditions
V
DD
= 2.7V
V
DD
= 2.7V
V
DD
= 2.3V, I
IN
= -18mA
-0.3
1.7
0.7
-0.7
Minimum
Typical
(2)
Maximum
±5
±5
-1.2
3.6
Units
µA
µA
V
V
V
V
V
V
V
NOTE 1: See
Recommended Operating Range
table.
NOTE 2: Typical values are at V
DD
= 2.5V, +25°C ambient.
NOTE 3: For A[1:2] single-ended operation, nA[1:2] is tied to a DC reference voltage.
Table 4C. Differential DC Characteristics
(1)
,
T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
IK
V
IN
V
DIF
V
CM
Parameter
Input High Current
Input Low Current
Clamp Diode Voltage
DC Input Voltage
DC Differential Voltage
(3)
DC Common Mode Input
Voltage
Test Conditions
V
DD
= 2.7V
V
DD
= 2.7V
V
DD
= 2.3V, I
IN
= -18mA
-0.3
0.1
0.05
V
DD
-0.7
Minimum
Typical
(2)
Maximum
±5
±5
-1.2
3.6
Units
µA
µA
V
V
V
V
NOTE 1: See
Recommended Operating Range
table.
NOTE 2: Typical values are at V
DD
= 2.5V, +25°C ambient.
NOTE 3: V
DIF
specifies the minimum input differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is
the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
NOTE 4: V
CM
specifies the maximum allowable range of (V
TR
+ V
CP
) /2.
IDT8R9306NLI REVISION D AUGUST 21, 2013
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©2013 Integrated Device Technology, Inc.
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