8-output 1.8V PCIe Gen1/2/3
Zero-Delay/Fan-out Buffer (ZDB/FOB)
9DBV0831
DATASHEET
Description
The 9DBV0831 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It can also be used for
50M or 125M Ethernet Applications via software frequency
selection. The device has 8 output enables for clock
management, and 3 selectable SMBus addresses.
Features/Benefits
•
LP-HCSL outputs save 16 resistors; minimal board space
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and BOM cost
62mW typical power consumption in PLL mode; minimal
power consumption
Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
•
8 – 1-200Hz Low-Power (LP) HCSL DIF pairs
w/Z
O
=100ohms
Key Specifications
•
•
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DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF
additive
phase jitter is <100fs rms for PCIe Gen3
DIF
additive
phase jitter <300fs rms for 12k-20MHz
Block Diagram
vOE(7:0)#
8
DIF7
CLK_IN
CLK_IN#
DIF6
SS-
Compatible
PLL
DIF5
DIF4
DIF3
CONTROL
LOGIC
DIF2
DIF1
DIF0
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
9DBV0831 REVISION H 04/28/16
1
©2016 Integrated Device Technology, Inc.
9DBV0831 DATASHEET
Pin Configuration
^CKPWRGD_PD#
VDD1.8
VDDIO
VDDIO
vOE7#
vOE6#
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri
^vHIBW_BYPM_LOBW#
FB_DNC
FB_DNC#
VDDR1.8
CLK_IN
CLK_IN#
GNDR
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
1
2
3
4
5
6
7
8
9
10
11
12
vOE0#
VDDIO
36
35
34
33
32
31
30
29
28
27
26
25
DIF2
DIF2#
DIF5#
DIF5
vOE4#
DIF4#
DIF4
VDDIO
VDDA1.8
GNDA
vOE3#
DIF3#
DIF3
vOE2#
9DBV0831
EPAD should be
connected to GND
13 14 15 16 17 18 19 20 21 22 23 24
DIF0#
vOE1#
DIF1#
VDD1.8
VDDIO
GND
DIF0
DIF1
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up
AND pull
down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+
Read/Write bit
x
x
x
Power Management Table
SMBus
DIFx
OEx# Pin
OEx bit
True O/P
Comp. O/P
0
X
X
X
Low
Low
1
Running
0
X
Low
Low
1
Running
1
0
Running
Running
1
Running
1
1
Low
Low
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
CKPWRGD_PD#
CLK_IN
PLL
Off
On
1
On
1
On
1
8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB) 2
vOE5#
DIF7#
DIF6#
GND
DIF7
DIF6
REVISION H 04/28/16
9DBV0831 DATASHEET
Power Connections
Pin Number
VDD
5
12
20, 31, 38
30
13, 21, 31,
39, 47
VDDIO
GND
8
9
22, 29, 40
29
Description
Input
receiver
analog
Digital Power
DIF outputs
PLL Analog
Frequency Select Table
FSEL
Byte3 [4:3]
00 (Default)
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
REVISION H 04/28/16
3
8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB)
9DBV0831 DATASHEET
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
TYPE
DESCRIPTION
LATCHED
vSADR_tri
Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
^vHIBW_BYPM_LOBW#
IN
See PLL Operating Mode Table for Details.
True clock of differential feedback. The feedback output and feedback input are
FB_DNC
DNC
connected internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback
FB_DNC#
DNC
input are connected internally on this pin. Do not connect anything to this pin.
VDDR1.8
CLK_IN
CLK_IN#
GNDR
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
VDDIO
vOE0#
DIF0
DIF0#
vOE1#
DIF1
DIF1#
VDD1.8
VDDIO
GND
DIF2
DIF2#
vOE2#
DIF3
DIF3#
vOE3#
GNDA
VDDA1.8
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDD1.8
PWR
IN
IN
GND
GND
IN
I/O
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
GND
OUT
OUT
IN
OUT
OUT
IN
GND
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
1.8V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.8V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominal 1.8V
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
1.8V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 1.8V
REVISION H 04/28/16
PIN NAME
8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB) 4
9DBV0831 DATASHEET
Pin Descriptions (cont.)
PIN #
39
40
41
42
43
44
45
46
47
48
49
PIN NAME
VDDIO
GND
DIF6
DIF6#
vOE6#
DIF7
DIF7#
vOE7#
VDDIO
^CKPWRGD_PD#
EPAD
TYPE
PWR
GND
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
GND
DESCRIPTION
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
Connect to Ground
REVISION H 04/28/16
5
8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB)
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