FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-
LVDS/LVCMOS FREQUENCY SYNTHESIZER
ICS8440259D-45
G
ENERAL
D
ESCRIPTION
The ICS8440259D-45 is a 9 output synthesizer
optimized to generate Gigabit and 10 Gigabit
HiPerClockS™
Ethernet clocks and is a member of the HiPerClockS™
family of high performance clock solutions from IDT.
Using a 25MHz, 18pF parallel resonant crystal, the
device will generate both 156.25MHz, 125MHz and 3.90625MHz
clocks with mixed LVDS and LVCMOS/LVTTL output levels. The
ICS8440259D-45 uses IDT’s 3
rd
generation low phase noise VCO
technology and can achieve <1ps typical rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS8440259D-45 is
packaged in a small, 5mm x 5mm VFQFN package that is optimum
for applications with space limitations.
F
EATURES
•
One differential LVDS output at 156.25MHz or 125MHz
Four differential LVDS outputs at 125MHz
Three LVCMOS/LVTTL single-ended outputs at 125MHz
One LVCMOS/LVTTL single-ended output at 3.90625MHz
•
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input and PLL bypass from a single select pin
•
VCO range: 510MHz - 650MHz
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.34ps (typical), LVDS output
•
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.31ps (typical), LVDS output
•
Full 3.3V supply mode
•
0°C to 70°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
IC
S
B
LOCK
D
IAGRAM
nPLL_BYPASS
Pullup
F_SEL
Pulldown
REF_CLK
Pulldown
25MHz
0
0
Q0
nQ0
XTAL_IN
Phase
Detector
1
VCO
490-680MHz
÷5
÷4
1
OSC
XTAL_OUT
0
Q1
nQ1
Q2
nQ2
P
IN
A
SSIGNMENT
XTAL_OUT
REF_CLK
XTAL_IN
F_SEL
GND
V
DD
÷5
nPLL_BYPASS
1
÷25
V
DDA
Q3
nQ3
32 31 30 29 28 27 26 25
Q0
nQ0
GND
Q1
nQ1
V
DDO
_
LVDS
Q2
nQ2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
DDO
_LVDS
GND
nQ4
GND
nQ3
V
DD
Q3
Q4
24
23
Q8
V
DDO
_
LVCMOS
Q7
GND
Q6
V
DDO
_
LVCMOS
Q5
GND
Q4
nQ4
Q5
ICS8440259D-45
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
22
21
20
19
18
17
Q6
Q7
÷32
Q8
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
1
ICS8440259DK-45 REV. A FEBRUARY 26, 2009
ICS8440259D-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 9, 15,
17, 21, 32
4, 5
6, 12
7, 8
10, 11
13, 14
16, 2 7
18, 20,
2 2, 24
19, 23
25
26
28
Name
Q0, nQ0
GND
Q1, nQ1
V
DDO_LVDS
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
DD
Q5, Q6,
Q7, Q8
V
DDO_LVCMOS
V
DDA
nPLL_BYPASS
F_SEL
Type
Output
Power
Output
Power
Output
Output
Output
Power
Output
Power
Power
Input
Input
Description
Differential clock outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Output supply pins for Qx/nQx LVDS outputs.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Core supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply pins for Q5:Q8 LVCMOS outputs.
Analog supply pin.
Input select and PLL bypass control pin. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Pulldown Frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
29
REF_CLK
Input
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
30,
XTAL_IN,
Crystal oscillator interface. XTAL_OUT is the output.
Input
31
XTAL_OUT
XTAL_IN is the input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance
Input Pulldown Resistor
Output Impedance
Q5:Q8
Test Conditions
Minimum
Typical
4
V
DD,
V
DDO_LVCMOS
= 3.465V
15
51
25
Maximum
Units
pF
pF
kΩ
Ω
T
ABLE
3A. F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
F_SEL
0
1
Input
Output Divider
÷5
÷4
Outputs
Q0/nQ0 Frequency
125MHz (default)
156.25MHz
T
ABLE
3B. PLL B
YPASS AND
I
NPUT
S
ELECT
F
UNCTION
T
ABLE
nPLL_BYPASS
0
1
Inputs
PLL Bypass
PLL Bypassed
PLL Enabled
Input Selected
REF_CLK
XTAL_IN/XTAL_OUT (default)
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
2
ICS8440259DK-45 REV. A FEBRUARY 26, 2009
ICS8440259D-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
10mA
15mA
-40°C to +85°C
-65°C to 150°C
37°C/W (0 mps)
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO_LVCMOS
+ 0.5V
NOTE:
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the
DC Characteristics
or
AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO_LVCMOS
= V
DDO_LVDS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO_LVCMOS,
V
DDO_LVDS
I
DD
I
DDA
I
DDO_LVCMOS
I
DDO_LVDS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
LVCMOS Output Supply Current
LVDS Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.35
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
118
35
10
160
Units
V
V
V
mA
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
REF_CLK (PD)
nPLL_BYPASS (PU)
REF_CLK (PD)
I
IL
Input Low Current
nPLL_BYPASS (PU)
V
OH
V
DD
= 3.465V, V
IN
= 0V
-150
µA
V
0.5
V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
Output High Voltage;
Q5:Q8
I
OH
= -12mA
2.6
NOTE 1
Output Low Voltage;
Q5:Q8
I
OL
= 12mA
V
OL
NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO_LVCMOS
/2. See Parameter Measurement Information,
Output Load Test Circuit diagram.
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
3
ICS8440259DK-45 REV. A FEBRUARY 26, 2009
ICS8440259D-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO_LVDS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.25
1.35
Test Conditions
Minimum
300
Typical
400
Maximum
545
50
1.5
50
Units
mV
mV
V
mV
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
25
50
7
Maximum
Units
MHz
Ω
pF
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDO_LVCMOS
= V
DDO_LVDS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
Parameter
Q0/nQ0:Q4/nQ4
f
OUT
Output
Frequency
Q5:Q7
Q8
Q0/nQ0
Q[1:4]/nQ[1:4]
RMS Phase Jitter
(Random);
NOTE 1
Q[0:4]/nQ[0:4]
Q0/nQ0
Q5:Q7
Q[0:4]/nQ[0:4]
(NOTE 2)
Q[0:4]/nQ[0:4]
t
R
/ t
F
Output
Rise/Fall Time
Q0/nQ0
Q5:Q7
Q8 (NOTE 2)
Q[0:4]/nQ[0:4]
odc
Output
Duty Cycle,
PLL Mode
Test Conditions
F_SEL = 0 (default)
F_SEL = 0 (default)
F_SEL = 0 (default)
F_SEL = 1
F_SEL = 1
125MHz, (1.875MHz - 20MHz)
156.25MHz,
(1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
PLL Mode, 125MHz,
30% to 70%
PLL Mode, 125MHz,
20% to 80%
PLL Mode, 156.25MHz,
20% to 80%
PLL Mode, 125MHz,
20% to 80%
3.90625MHz, 20% to 80%
125MHz
Minimum
Typical
125
125
3.90625
156.25
125
0.34
0.31
0.48
1.00E-10
1.50E-10
2.50E-10
4.00E-10
6.50E-10
47
1.02E-09
5.50E-10
3.75E-10
1.15E-09
1.35E-09
53
Maximum
Units
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
s
s
s
s
s
%
t
jit(Ø)
Q0/nQ0
156.25MHz
48
52
%
Q5:Q7
125MHz
45
55
%
Q8
3.90625MHz
49
51
%
Q[0:4]/nQ[0:4]
125MHz
45
55
%
Output
Q0/nQ0
156.25MHz
45
55
%
o dc
Duty Cycle,
Q5:Q7
125MHz
45
55
%
BYPASS Mode
Q8
3.90625MHz
49
51
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Please refer to the Phase Noise Plots.
NOTE 2: Output loaded with 100
Ω
differential and 15pF loads.
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
4
ICS8440259DK-45 REV. A FEBRUARY 26, 2009
ICS8440259D-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
(LVDS @ 3.3V)
N
OISE
P
OWER
dBc
Hz
O
FFSET
F
REQUENCY
(H
Z
)
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
5
ICS8440259DK-45 REV. A FEBRUARY 26, 2009
Microcontroller MCU
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