MC145170DT1 datasheet, PDF - EEWORLD Datasheet

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MC145170DT1: DescriptionPLL Frequency Synthesizer with Serial Interface CMOS; CategoryAnalog mixed-signal IC The signal circuit; File Size234KB，27 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MC145170DT1 Overview

PLL Frequency Synthesizer with Serial Interface CMOS

MC145170DT1 Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP16,.25
Contacts	16
Reach Compliance Code	unknown
Analog Integrated Circuits - Other Types	PLL FREQUENCY SYNTHESIZER
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	5 mm
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm

MC145170DT1 Preview

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MC145170–1/D

MC145170-1

Advance Information

PLL Frequency Synthesizer

with Serial Interface

CMOS

The new MC145170–1 is pin–for–pin compatible with the MC145170. A

comparison of the two parts is shown in the table below. The MC145170–1 is

recommended for new designs.

The MC145170–1 is a single–chip synthesizer capable of direct usage in the

MF, HF, and VHF bands. A special architecture makes this PLL the easiest to

program in the industry. Either a bit– or byte–oriented format may be used. Due

to the patented BitGrabber™ registers, no address/steering bits are required for

random access

of the three registers. Thus, tuning can be accomplished via a

2–byte serial transfer to the 16–bit N register.

The device features fully programmable R and N counters, an amplifier at the

fin pin, on–chip support of an external crystal, a programmable reference

output, and both single– and double–ended phase detectors with linear transfer

functions (no dead zones). A configuration (C) register allows the part to be

configured to meet various applications. A patented feature allows the C

In order to reduce lock times and prevent erroneous data from being loaded

into the counters, a patented jam–load feature is included. Whenever a new

divide ratio is loaded into the N register, both the N and R counters are

jam–loaded with their respective values and begin counting down together. The

phase detectors are also initialized during the jam load.

•

Operating Voltage Range: 2.5 to 5.5 V

•

Maximum Operating Frequency:

185 MHz @ Vin = 500 mV p–p, 4.5 V Minimum Supply

100 MHz @ Vin = 500 mV p–p, 3.0 V Minimum Supply

•

Operating Supply Current: 0.6 mA @ 3 V, 30 MHz

1.5 mA @ 3 V, 100 MHz

3.0 mA @ 5 V, 50 MHz

5.8 mA @ 5 V, 185 MHz

•

Operating Temperature Range: – 40 to 85°C

•

R Counter Division Range: 1 and 5 to 32,767

•

N Counter Division Range: 40 to 65,535

•

Direct Interface to Motorola SPI and National MICROWIRE™ Serial Data

Ports

•

Chip Complexity: 4800 FETs or 1200 Equivalent Gates

•

See Application Note AN1207/D

COMPARISION OF THE PLL FREQUENCY SYNTHESIZERS

Parameter

Technology

Maximum Frequency with 5 V

10% Supply, fin

Maximum Frequency with 5 V

10% Supply, OSCin

Maximum Supply Voltage

Maximum Input Capacitance, fin

MC145170–1

1.2

µm

CMOS

185 MHz

25 MHz

5.5 V

7 pF

MC145170

1.5

µm

CMOS

160 MHz

20 MHz

6.0 V

5 pF

P SUFFIX

PLASTIC DIP

CASE 648

D SUFFIX

SOG PACKAGE

CASE 751B

DT SUFFIX

TSSOP

CASE 948C

ORDERING INFORMATION

MC145170P1 Plastic DIP

MC145170D1 SOG Package

MC145170DT1 TSSOP

PIN ASSIGNMENT

OSCin

OSCout

REFout

fin

Din

ENB

CLK

Dout

VDD

PDout

VSS

This document contains information on a new product. Specifications and information herein are subject to change without notice.

BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.

REV 1

3/96

Motorola, Inc. 1996

MOTOROLA

MC145170–1

BLOCK DIAGRAM

OSCin

OSCout

OSC

15–STAGE R COUNTER

fR CONTROL

REFout

4–STAGE

REFERENCE

DIVIDER

BitGrabber R REGISTER

15 BITS

LOCK DETECTOR

AND CONTROL

CLK

Din

Dout

SHIFT

AND

CONTROL

LOGIC

BitGrabber C REGISTER

8 BITS

PHASE/FREQUENCY

DETECTOR A AND CONTROL

PDout

POR

ENB

PHASE/FREQUENCY

DETECTOR B AND CONTROL

BitGrabber N REGISTER

16 BITS

fin 4

fV CONTROL

PIN 16 = VDD

PIN 12 = VSS

INPUT

AMP

16–STAGE N COUNTER

MAXIMUM RATINGS*

(Voltages Referenced to VSS)

Symbol

VDD

Vin

Vout

Iin

Iout

IDD

Tstg

Parameter

DC Supply Voltage

DC Input Voltage

DC Output Voltage

DC Input Current, per Pin

DC Output Current, per Pin

DC Supply Current, VDD and VSS Pins

Power Dissipation, per Package

Storage Temperature

Lead Temperature, 1 mm from Case

for 10 seconds

Value

– 0.5 to + 5.5

– 0.5 to VDD + 0.5

300

– 65 to + 150

260

Unit

°C

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

operation, Vin and Vout should be constrained

to the range VSS

≤

(Vin or Vout)

≤

VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD). Unused outputs must be left open.

* Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Electrical Characteristics

tables or Pin Descriptions section.

MC145170–1

MOTOROLA

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to VSS, TA = – 40 to + 85°C)

Symbol

VDD

VIL

Parameter

Power Supply Voltage Range

Maximum Low–Level Input Voltage*

(Din, CLK, ENB, fin)

Minimum High–Level Input Voltage*

(Din, CLK, ENB, fin)

Minimum Hysteresis Voltage (CLK, ENB)

Maximum Low–Level Output Voltage

(Any Output)

Minimum High–Level Output Voltage

(Any Output)

Minimum Low–Level Output Current

(PDout, REFout, fR, fV, LD,

Minimum High–Level Output Current

(PDout, REFout, fR, fV, LD,

Minimum Low–Level Output Current

(Dout)

Minimum High–Level Output Current

(Dout)

Maximum Input Leakage Current

(Din, CLK, ENB, OSCin)

Maximum Input Current

(fin)

Maximum Output Leakage Current (PDout)

(Dout)

IDD

Idd

Maximum Quiescent Supply Current

Maximum Operating Supply Current

Vin = VDD or VSS; Outputs Open;

Excluding fin Amp Input Current Component

fin = 500 mV p–p;

OSCin = 1 MHz @ 1 V p–p;

LD, fR, fV, REFout = Inactive and No Connect;

OSCout,

R, PDout = No Connect;

Din, ENB, CLK = VDD or VSS

Iout = 20

µA

Iout = – 20

µA

Vout = 0.3 V

Vout = 0.4 V

Vout = 0.5 V

Vout = 2.2 V

Vout = 4.1 V

Vout = 5.0 V

Vout = 0.4 V

Vout = 4.1 V

Vin = VDD or VSS

Vin = VDD or VSS,

Output in High–Impedance State

dc Coupling to fin

Test Condition

VDD

—

2.5

4.5

5.5

2.5

4.5

5.5

2.5

5.5

2.5

5.5

2.5

5.5

2.5

4.5

5.5

2.5

4.5

5.5

4.5

5.5

—

Guaranteed

Limit

2.5 to 5.5

0.50

1.35

1.65

2.00

3.15

3.85

0.15

0.20

0.1

2.4

5.4

0.12

0.36

– 0.12

– 0.36

1.6

– 1.6

1.0

120

100

Unit

VIH

dc Coupling to fin

VHys

VOL

VOH

IOL

IOH

IOL

IOH

Iin

IOZ

µA

* When dc coupling to the OSCin pin is used, the pin must be driven rail–to–rail. In this case, OSCout should be floated.

** The nominal values at 3 V are 0.6 mA @ 30 MHz, and 1.5 mA @ 100 MHz. The nominal values at 5 V are 3.0 mA @ 50 MHz, and 5.8 mA

@ 185 MHz. These are not guaranteed limits.

MOTOROLA

MC145170–1

AC INTERFACE CHARACTERISTICS

( TA = – 40 to + 85°C, CL = 50 pF, Input tr = tf = 10 ns unless otherwise indicated)

Symbol

fclk

Parameter

Serial Data Clock Frequency (Note: Refer to Clock tw Below)

Figure

No.

VDD

2.5

4.5

5.5

2.5

4.5

5.5

2.5

4.5

5.5

2.5

4.5

5.5

2.5

4.5

5.5

2.5

4.5

5.5

—

Guaranteed

Limit

dc to 3.0

dc to 4.0

150

300

200

0 to 200

0 to 100

150

900

150

Unit

MHz

tPLH, tPHL

Maximum Propagation Delay, CLK to Dout

1, 5

tPLZ, tPHZ

Maximum Disable Time, Dout Active to High Impedance

2, 6

tPZL, tPZH

Access Time, Dout High Impedance to Active

2, 6

tTLH, tTHL

Maximum Output Transition Time, Dout

CL = 50 pF

1, 5

CL = 200 pF

1, 5

Cin

Cout

Maximum Input Capacitance – Din, ENB, CLK

Maximum Output Capacitance – Dout

TIMING REQUIREMENTS

( TA = – 40 to + 85°C, Input tr = tf = 10 ns unless otherwise indicated)

Symbol

tsu, th

Parameter

Minimum Setup and Hold Times, Din vs CLK

Figure

No.

VDD

2.5

4.5

5.5

2.5

4.5

5.5

2.5

4.5

5.5

2.5

4.5

5.5

2.5

4.5

5.5

Guaranteed

Limit

135

100

400

300

166

125

100

Unit

tsu, th, trec

Minimum Setup, Hold, and Recovery Times, ENB vs CLK

tw(H)

Minimum Inactive–High Pulse Width, ENB

Minimum Pulse Width, CLK

tr, tf

Maximum Input Rise and Fall Times, CLK

µs

MC145170–1

MOTOROLA

SWITCHING WAVEFORMS

90%

CLK 50%

10%

1/fclk

tPLH

Dout

90%

50%

10%

tTLH

tTHL

tPHL

tPZH

Dout

50%

tPHZ

90%

VSS

HIGH

IMPEDANCE

Dout

VDD

VSS

ENB

50%

tPZL

50%

VDD

VSS

tPLZ

10%

HIGH

IMPEDANCE

VDD

Figure 1.

Figure 2.

tw(H)

VALID

VDD

Din

50%

VSS

tsu

CLK

50%

VSS

VDD

tsu

CLK

trec

VDD

50%

FIRST

CLK

LAST

CLK

VSS

ENB

50%

VSS

VDD

Figure 3.

Figure 4.

TEST POINT

7.5 kΩ

DEVICE

UNDER

TEST

DEVICE

UNDER

TEST

CONNECT TO VDD

WHEN TESTING tPLZ

AND tPZL. CONNECT TO

VSS WHEN TESTING

tPHZ AND tPZH.

* Includes all probe and fixture capacitance.

Figure 5. Test Circuit

Figure 6. Test Circuit

MOTOROLA

MC145170–1

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MC145170DT1 Related Products

	MC145170DT1	MC145170-1	MC145170D1	MC145170P1
Description	PLL Frequency Synthesizer with Serial Interface CMOS	PLL Frequency Synthesizer with Serial Interface CMOS	PLL Frequency Synthesizer with Serial Interface CMOS	PLL Frequency Synthesizer with Serial Interface CMOS
Maker	Motorola ( NXP )	-	Motorola ( NXP )	Motorola ( NXP )
package instruction	TSSOP, TSSOP16,.25	-	SOG-16	PLASTIC, DIP-16
Reach Compliance Code	unknown	-	unknow	unknown
Analog Integrated Circuits - Other Types	PLL FREQUENCY SYNTHESIZER	-	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER
JESD-30 code	R-PDSO-G16	-	R-PDSO-G16	R-PDIP-T16
JESD-609 code	e0	-	e0	e0
length	5 mm	-	9.9 mm	19.175 mm
Number of functions	1	-	1	1
Number of terminals	16	-	16	16
Maximum operating temperature	85 °C	-	85 °C	85 °C
Minimum operating temperature	-40 °C	-	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	-	SOP	DIP
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	SMALL OUTLINE	IN-LINE
Certification status	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	-	1.75 mm	4.44 mm
Maximum supply voltage (Vsup)	5.5 V	-	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2.5 V	-	2.5 V	2.5 V
Nominal supply voltage (Vsup)	5 V	-	5 V	5 V
surface mount	YES	-	YES	NO
technology	CMOS	-	CMOS	CMOS
Temperature level	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	-	GULL WING	THROUGH-HOLE
Terminal pitch	0.65 mm	-	1.27 mm	2.54 mm
Terminal location	DUAL	-	DUAL	DUAL
width	4.4 mm	-	3.9 mm	7.62 mm

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