MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145170–1/D
MC145170-1
Advance Information
PLL Frequency Synthesizer
with Serial Interface
CMOS
The new MC145170–1 is pin–for–pin compatible with the MC145170. A
comparison of the two parts is shown in the table below. The MC145170–1 is
recommended for new designs.
The MC145170–1 is a single–chip synthesizer capable of direct usage in the
MF, HF, and VHF bands. A special architecture makes this PLL the easiest to
program in the industry. Either a bit– or byte–oriented format may be used. Due
to the patented BitGrabber™ registers, no address/steering bits are required for
random access
of the three registers. Thus, tuning can be accomplished via a
2–byte serial transfer to the 16–bit N register.
The device features fully programmable R and N counters, an amplifier at the
fin pin, on–chip support of an external crystal, a programmable reference
output, and both single– and double–ended phase detectors with linear transfer
functions (no dead zones). A configuration (C) register allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing noise and interference.
In order to reduce lock times and prevent erroneous data from being loaded
into the counters, a patented jam–load feature is included. Whenever a new
divide ratio is loaded into the N register, both the N and R counters are
jam–loaded with their respective values and begin counting down together. The
phase detectors are also initialized during the jam load.
•
Operating Voltage Range: 2.5 to 5.5 V
•
Maximum Operating Frequency:
185 MHz @ Vin = 500 mV p–p, 4.5 V Minimum Supply
100 MHz @ Vin = 500 mV p–p, 3.0 V Minimum Supply
•
Operating Supply Current: 0.6 mA @ 3 V, 30 MHz
1.5 mA @ 3 V, 100 MHz
3.0 mA @ 5 V, 50 MHz
5.8 mA @ 5 V, 185 MHz
•
Operating Temperature Range: – 40 to 85°C
•
R Counter Division Range: 1 and 5 to 32,767
•
N Counter Division Range: 40 to 65,535
•
Direct Interface to Motorola SPI and National MICROWIRE™ Serial Data
Ports
•
Chip Complexity: 4800 FETs or 1200 Equivalent Gates
•
See Application Note AN1207/D
COMPARISION OF THE PLL FREQUENCY SYNTHESIZERS
Parameter
Technology
Maximum Frequency with 5 V
±
10% Supply, fin
Maximum Frequency with 5 V
±
10% Supply, OSCin
Maximum Supply Voltage
Maximum Input Capacitance, fin
MC145170–1
1.2
µm
CMOS
185 MHz
25 MHz
5.5 V
7 pF
MC145170
1.5
µm
CMOS
160 MHz
20 MHz
6.0 V
5 pF
P SUFFIX
PLASTIC DIP
CASE 648
16
1
16
1
D SUFFIX
SOG PACKAGE
CASE 751B
16
1
DT SUFFIX
TSSOP
CASE 948C
ORDERING INFORMATION
MC145170P1 Plastic DIP
MC145170D1 SOG Package
MC145170DT1 TSSOP
PIN ASSIGNMENT
OSCin
OSCout
REFout
fin
Din
ENB
CLK
Dout
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
φ
V
φ
R
PDout
VSS
LD
fV
fR
This document contains information on a new product. Specifications and information herein are subject to change without notice.
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 1
3/96
©
Motorola, Inc. 1996
MOTOROLA
MC145170–1
1
BLOCK DIAGRAM
OSCin
OSCout
1
2
OSC
15–STAGE R COUNTER
fR CONTROL
9
fR
15
REFout
3
4–STAGE
REFERENCE
DIVIDER
BitGrabber R REGISTER
15 BITS
3
LOCK DETECTOR
AND CONTROL
11
LD
CLK
Din
Dout
6
7
5
SHIFT
REGISTER
AND
CONTROL
LOGIC
BitGrabber C REGISTER
8 BITS
16
PHASE/FREQUENCY
DETECTOR A AND CONTROL
13
PDout
8
POR
ENB
PHASE/FREQUENCY
DETECTOR B AND CONTROL
BitGrabber N REGISTER
16 BITS
16
fin 4
10
14
15
φ
R
φ
V
fV CONTROL
PIN 16 = VDD
PIN 12 = VSS
fV
INPUT
AMP
16–STAGE N COUNTER
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Vin
Vout
Iin
Iout
IDD
PD
Tstg
TL
Parameter
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VDD and VSS Pins
Power Dissipation, per Package
Storage Temperature
Lead Temperature, 1 mm from Case
for 10 seconds
Value
– 0.5 to + 5.5
– 0.5 to VDD + 0.5
– 0.5 to VDD + 0.5
±
10
±
20
±
30
300
– 65 to + 150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
MC145170–1
2
MOTOROLA
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, TA = – 40 to + 85°C)
Symbol
VDD
VIL
Parameter
Power Supply Voltage Range
Maximum Low–Level Input Voltage*
(Din, CLK, ENB, fin)
Minimum High–Level Input Voltage*
(Din, CLK, ENB, fin)
Minimum Hysteresis Voltage (CLK, ENB)
Maximum Low–Level Output Voltage
(Any Output)
Minimum High–Level Output Voltage
(Any Output)
Minimum Low–Level Output Current
(PDout, REFout, fR, fV, LD,
φ
R,
φ
V)
Minimum High–Level Output Current
(PDout, REFout, fR, fV, LD,
φ
R,
φ
V)
Minimum Low–Level Output Current
(Dout)
Minimum High–Level Output Current
(Dout)
Maximum Input Leakage Current
(Din, CLK, ENB, OSCin)
Maximum Input Current
(fin)
Maximum Output Leakage Current (PDout)
(Dout)
IDD
Idd
Maximum Quiescent Supply Current
Maximum Operating Supply Current
Vin = VDD or VSS; Outputs Open;
Excluding fin Amp Input Current Component
fin = 500 mV p–p;
OSCin = 1 MHz @ 1 V p–p;
LD, fR, fV, REFout = Inactive and No Connect;
OSCout,
φ
V,
φ
R, PDout = No Connect;
Din, ENB, CLK = VDD or VSS
Iout = 20
µA
Iout = – 20
µA
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
Vout = 2.2 V
Vout = 4.1 V
Vout = 5.0 V
Vout = 0.4 V
Vout = 4.1 V
Vin = VDD or VSS
Vin = VDD or VSS
Vin = VDD or VSS,
Output in High–Impedance State
dc Coupling to fin
Test Condition
VDD
V
—
2.5
4.5
5.5
2.5
4.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
4.5
5.5
2.5
4.5
5.5
4.5
4.5
5.5
5.5
5.5
5.5
5.5
—
Guaranteed
Limit
2.5 to 5.5
0.50
1.35
1.65
2.00
3.15
3.85
0.15
0.20
0.1
0.1
2.4
5.4
0.12
0.36
0.36
– 0.12
– 0.36
– 0.36
1.6
– 1.6
±
1.0
±
120
±
100
±
5
100
**
Unit
V
V
VIH
dc Coupling to fin
V
VHys
VOL
VOH
IOL
V
V
V
mA
IOH
mA
IOL
IOH
Iin
Iin
IOZ
mA
mA
µA
µA
nA
µA
µA
mA
* When dc coupling to the OSCin pin is used, the pin must be driven rail–to–rail. In this case, OSCout should be floated.
** The nominal values at 3 V are 0.6 mA @ 30 MHz, and 1.5 mA @ 100 MHz. The nominal values at 5 V are 3.0 mA @ 50 MHz, and 5.8 mA
@ 185 MHz. These are not guaranteed limits.
MOTOROLA
MC145170–1
3
AC INTERFACE CHARACTERISTICS
( TA = – 40 to + 85°C, CL = 50 pF, Input tr = tf = 10 ns unless otherwise indicated)
Symbol
fclk
Parameter
Serial Data Clock Frequency (Note: Refer to Clock tw Below)
Figure
No.
1
VDD
V
2.5
4.5
5.5
2.5
4.5
5.5
2.5
4.5
5.5
2.5
4.5
5.5
2.5
4.5
5.5
2.5
4.5
5.5
—
—
Guaranteed
Limit
dc to 3.0
dc to 4.0
dc to 4.0
150
85
85
300
200
200
0 to 200
0 to 100
0 to 100
150
50
50
900
150
150
10
10
Unit
MHz
tPLH, tPHL
Maximum Propagation Delay, CLK to Dout
1, 5
ns
tPLZ, tPHZ
Maximum Disable Time, Dout Active to High Impedance
2, 6
ns
tPZL, tPZH
Access Time, Dout High Impedance to Active
2, 6
ns
tTLH, tTHL
Maximum Output Transition Time, Dout
CL = 50 pF
1, 5
ns
CL = 200 pF
1, 5
ns
Cin
Cout
Maximum Input Capacitance – Din, ENB, CLK
Maximum Output Capacitance – Dout
pF
pF
TIMING REQUIREMENTS
( TA = – 40 to + 85°C, Input tr = tf = 10 ns unless otherwise indicated)
Symbol
tsu, th
Parameter
Minimum Setup and Hold Times, Din vs CLK
Figure
No.
3
VDD
V
2.5
4.5
5.5
2.5
4.5
5.5
2.5
4.5
5.5
2.5
4.5
5.5
2.5
4.5
5.5
Guaranteed
Limit
55
40
40
135
100
100
400
300
300
166
125
125
100
100
100
Unit
ns
tsu, th, trec
Minimum Setup, Hold, and Recovery Times, ENB vs CLK
4
ns
tw(H)
Minimum Inactive–High Pulse Width, ENB
4
ns
tw
Minimum Pulse Width, CLK
1
ns
tr, tf
Maximum Input Rise and Fall Times, CLK
1
µs
MC145170–1
4
MOTOROLA
SWITCHING WAVEFORMS
tf
90%
CLK 50%
10%
tw
1/fclk
tPLH
Dout
90%
50%
10%
tTLH
tTHL
tPHL
tPZH
Dout
50%
tPHZ
90%
VSS
HIGH
IMPEDANCE
tw
Dout
tr
VDD
VSS
ENB
50%
tPZL
50%
VDD
VSS
tPLZ
10%
HIGH
IMPEDANCE
VDD
Figure 1.
Figure 2.
tw(H)
VALID
VDD
Din
50%
VSS
tsu
CLK
th
50%
VSS
VDD
tsu
CLK
th
trec
VDD
50%
FIRST
CLK
LAST
CLK
VSS
ENB
50%
VSS
VDD
Figure 3.
Figure 4.
TEST POINT
TEST POINT
7.5 kΩ
DEVICE
UNDER
TEST
CL
*
DEVICE
UNDER
TEST
CL
*
CONNECT TO VDD
WHEN TESTING tPLZ
AND tPZL. CONNECT TO
VSS WHEN TESTING
tPHZ AND tPZH.
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
Figure 5. Test Circuit
Figure 6. Test Circuit
MOTOROLA
MC145170–1
5
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