AN1568/D
Interfacing Between LVDS
and ECL
Prepared by: Paul Lee
Logic Applications Engineer
ON Semiconductor
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APPLICATION NOTE
Introduction
Recent growth in high−speed data transmission between
high−speed ICs demand more bandwidth than ever before
while still maintaining high performance, low power
consumption and good noise immunity. Emitter Coupled
Logic (ECL) recognized the challenge and provided high
performance and good noise immune devices. ECL
migrated toward low voltages to reduce the power
consumption and to keep up with current technology trends
by offering 3.3 V and 2.5 V Low Voltage ECL (LVECL)
devices.
LVDS (Low Voltage Differential Signaling) technology
also addresses the needs of current high performance
applications. LVDS as specified in ANSI/TIA/EIA−644 by
Data Transmission Interface committee TR30.2 and IEEE
1596.3 SCI−LVDS by IEEE Scalable Coherent Interface
standard (SCI) is a high speed, low power interface that is a
solution in many application areas. LVDS provides an
output swing of 250 mV to 400 mV with a DC offset of 1.2 V.
External resistor components are required for
board−to−board data transfer or clock distribution.
LVECL and LVDS are both differential voltage signals,
but with different output amplitude and offset. The purpose
of this documentation is to show the interfacing between
LVECL and LVDS. In addition, it gives interface
recommendations to and from 5.0 V supplied PECL devices
and negative supplied ECL or NECL
ECL levels
Today’s applications typically use ECL devices in the
PECL mode. PECL (Positive ECL) is nothing more than
supplying any ECL device with a positive power supply
(V
CC
= +5.0 V, V
EE
= 0 V). In addition, ECL uses differential
data transmission technology, which results in better noise
immunity. Since the common mode noise is coupled onto the
differential interconnect, it will be seen as a common mode
modulation and will be rejected.
With the trend towards low voltage systems, a new
generation of ECL circuitry has been developed. The Low
Voltage NECL (LVNECL) devices work using negative
–3.3 V or –2.5 V power supply, or more popular positive
power supplies, V
CC
= +3.3 V or +2.5 V and V
EE
= GND as
LVPECL. LVECL maintains 750 mV output swing with a
0.9 V offset from V
CC
, which makes them ideal as peripheral
components.
The temperature compensated (100EL, 100LVEL,
100EP, 100LVEP) output DC levels for the different supply
levels are shown in Table 1. ECL outputs are designed as an
open emitter, requiring a DC path to a more negative supply
than V
OL
. (see AND8020 for ECL Termination
information).
ECL standard DC input levels are also relative to V
CC
.
Many devices are available with Voltage Input HIGH
Common Mode Range (V
IHCMR
). These differential inputs
allow processing signals with small V
INPPMIN
(down to
200 mV, 150 mV or even 50 mV signal levels) within an
appropriate offset range. The V
IHCMR
ranges of ECL
devices are listed in each respective data sheets.
©
Semiconductor Components Industries, LLC, 2003
1
October, 2003 − Rev. 8
Publication Order Number:
AN1568/D
AN1568/D
Table 1. MC100EXXX/MC100ELXXX/LVELXXX/EPXXX/LVEPXXX
(T
A
= 0°C to +85°C)
Symbol
V
CC
V
EE
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
Parameter
Positive Supply Voltage
Negative Supply Voltage
Maximum Output HIGH Level
Typical Output HIGH Level
Minimum Output HIGH Level
Maximum Output LOW Level
Typical Output LOW Level
Minimum Output LOW Level
2.5 V LVPECL
(Note 1)
+2.5
GND
1.680
1.555
1.430
0.880
0.755
0.630
3.3 V LVPECL
(Note 1)
+3.3
GND
2.480
2.355
2.230
1.680
1.555
1.430
5.0 V PECL
(Note 1)
+5
GND
4.180
4.055
3.930
3.380
3.255
3.130
NECL
GND
−5.2, −4.5, −3.3 or −2.5
−0.820
−0.945
−1.070
−1.620
−1.745
−1.870
Unit
V
V
V
V
V
V
V
V
1. All levels vary 1:1 with V
CC
and loaded with 50
W
to V
CC
− 2.0 V.
LVDS Levels
As the name indicates, the LVDS main attribute is the low
voltage amplitude levels compared to other data
transmission standards, as shown in Figure 1. The LVDS
specification states 250 mV to 400 mV output swing for
driver/transmitter (V
OUTPP
). The low voltage swing levels
result in low power consumption while maintaining high
performance levels required by most users. In addition,
LVDS uses differential data transmission technology
equivalent to ECL. Furthermore, LVDS technology is not
dependent on specific power supply levels like ECL
technology. This signifies an easy migration path to lower
supply voltages such as 3.3 V, 2.5 V, or lower voltages while
still maintaining the same signaling levels and high
performance. ON Semiconductor currently provides a 2.5 V
1:5 dual differential LVDS Clock Driver/Receiver
(MC100EP210S).
Z = 50
W
LVDS
Z = 50
W
100
W
Figure 2. LVDS Output Definition
SIGNAL VOLTAGE
LVDS receivers require 200 mV minimum input swing
within the input voltage range of 0 V to 2.4 V and can tolerate
a minimum of
$1.0
V ground shift between the driver’s
ground and the receiver’s ground, since LVDS receivers
have a typical driver offset voltage of 1.2 V. The common
mode range of the LVDS receiver is 0.2 V to 2.2 V, and the
recommended LVDS receiver input voltage range is from
0 V to 2.4 V. Common mode range of LVDS is similar to the
theory of Voltage Input HIGH Common Mode Range
(V
IHCMR
) of ECL devices.
Currently more LVDS standards are being developed as
LVDS technology gains in popularity.
BLVDS
PECL
3.3 V LVPECL
2.5 V LVPECL
LVDS
3.3 V LVTTL/LVCMOS
Bus LVDS (BLVDS) was developed for multipoint
applications. This standard is targeted at heavily loaded back
planes, which reduces the impedance of the transmission
line by 50% or more. By providing increased drive current,
the double termination seen by the driver will be
compensated.
M−LVDS
NECL/LVNECL
Figure 1. Comparison of Output Voltage Levels
Standards (Figure not to Scale)
TIA TR30.2 standards group is developing another
multipoint LVDS application called Multipoint LVDS
(M−LVDS). The maximum data rate is 500 Mbps.
LVDS require a 100
W
load resistor between the
differential outputs to generate the Differential Output
Voltage (V
OD
) with a maximum current of 2.5 mA flowing
through the load resistor. This load resistor will terminate the
50
W
controlled characteristic impedance line, which
prevent reflections and reduces unwanted electromagnetic
emission (Figure 2).
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AN1568/D
GLVDS and SLVS
Ground referenced LVDS (GLVDS) is similar to LVDS
except the driver output voltage offset is nearer to ground.
The advantage of GLVDS is the use of very low power
supply voltages (0.5 V).
Similar standard to GLVDS is SLVS (Scalable
Low−Voltage Signaling for 400 mV) by JEDEC. The
interface is terminated to ground with 400mV swing and a
minimum supply voltage of 0.8 V.
LVDM
LVDM is designed for double 100
W−terminated
applications. The driver’s output current is two times the
standard LVDS, thus producing LVDS characteristic levels.
Table 2. LVDS LEVELS
LVDS
Specification
Symbol
Transmitter
V
PP
V
OS
R
L
I
OD
Receiver
Input Voltage
Range
Differential HIGH
Input Threshold
Differential LOW
Input Threshold
−100
0
2400
+100
−100
0
2400
+100
−50
−1000
Output Differen-
tial Voltage
Output Offset
Voltage
Load Resistor
Output Differen-
tial Current
2.5
250
1125
400
1275
240
1225
27
4.5
9
500
1375
50
17
9
480
300
Parameter
Min
Max
BLVDS
Specification
Min
Max
Interfacing
Common mode range inputs are capable of processing
signals with 150 mV to 400 mV amplitude. The ECL input
processes signals up to 1.0 V amplitude. The DC voltage
levels should be within the voltage input HIGH common
mode range (V
IHCMR
).
To interface between these two voltage levels, capacitive
coupling can be used. Only clock or coded signals should be
capacitively coupled. A capacitive coupling of NRZ signals
will cause problems, which can require a passive or active
interfacing.
M−LVDS
Specification
Min
Max
GLVDS
Specification
Min
Max
LVDM
Specification
Min
Max
Unit
Condition
650
2100
50
13
150
75
500
250
247
1.125
50
6
454
mV
mV
W
mA
100
Internal To Rx
Adjustable
3800
+50
−500
1000
+100
0
2400
+100
MV
mV
mV
V
gpd
< 950 mV
(Note 2)
V
gpd
< 950 mV
(Note 2)
V
gpd
< 950 mV
(Note 2)
−100
−100
2. Vgpd is the voltage of Ground Potential Delta across or between boards.
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AN1568/D
Capacitive Coupling LVDS to ECL
Capacitive Coupling LVDS to ECL Using V
BB
Several ECL devices provide an externally accessible
V
BB
(V
BB
≈
V
CC
–1.3V) reference voltage. This ECL
reference voltage can be used for differential capacitive
coupling. The 10 nF capacitor can be used to decouple V
BB
to GND. (Figure 3)
Z = 50
W
10 pF
In the layout for both interfaces, the resistors and the
capacitors should be located as close as possible to the ECL
input to insure reduced reflection and increased signal
integrity.
Capacitive Coupling ECL to LVDS
The ECL output requires a DC current path to V
EE
;
therefore, the pulldown termination resistors, R
T
, are
connected to V
EE
. The Thevenin resistor pair represent the
termination of the transmission line Z = R1 || R2 and
generates an appropriate DC offset level of 1.2 V. (Figure 5)
3.3 V
R1
130
W
Z = 50
W
10 pF
R1
130
W
LVDS
Z = 50
W
100
W
ECL
V
BB
1 kW
10 pF
1 kW
10 nF
ECL
Z = 50
W
10 pF
R2
80
W
LVDS
Figure 3. Capacitive Coupling LVDS to ECL
Using V
BB
R
T
R
T
R2
80
W
Capacitive Coupling LVDS to ECL with External
Biasing
V
EE
If V
BB
reference voltage is not available, equivalent DC
voltage can be generated using a resistor divider network.
The resistor values depend on V
CC
and V
EE
voltages
(Table 3). Stability is enhanced during null signal conditions
if a 50 mV differential voltage is maintained between the
divider networks. (Figure 4)
Table 3. Examples:
V
CC
= GND
V
CC
= GND
V
CC
= GND
V
EE
= −5.0 V
V
EE
= −3.3 V
V
EE
= −2.5 V
R1 = 1.2 kW
R1 = 680
W
R1 = 100
W
V
CC
R1
R2 = 3.4 kW
R2 = 1.0 kW
R2 = 90
W
Figure 5. Capacitive Coupling ECL to LVDS
An example of capacitive coupled LVPECL
(ECLinPS Plus™ Device) to LVDS is shown below.
(Figure 6)
2.5 V or 3.3 V
R3
3.9 kW
3.3 V
R3
3.9 kW
3.3 V
R2
43
W
LVPECL
R2
43
W
10 pF
LVDS
R1
Z = 50
W
10 pF
R1
237
W
ECL
10 pF
R4
R1
2 kW
237
W
R4
2 kW
LVDS
Z = 50
W
100
W
Figure 6. Capacitive Coupling LVPECL to LVDS
10 pF
R2
R2
Capacitive Coupling ECL to LVDS Using V
OS
Reference Voltage
V
EE
Figure 4. Capacitive Coupling LVDS to ECL with
External Biasing
Some LVDS devices supply external offset reference
voltage (V
OS
), which can be used for capacitive coupling.
When the transmission line is very short, a parallel
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AN1568/D
termination should be used and placed as close as possible
to the coupling capacitors. (Figure 7)
3.3 V
LVPECL
100 kW
Z = 50
W
10 pF
R
T
ECL
Z = 50
W
10 pF
1 kW
50
W
V
TT
V
OS
=
1.2 V
LVDS
R
T
Z
O
100
W
LVDS
2.5 V
Z
O
V
CC
50
W
1 kW
Figure 9. Interfacing 2.5 V LVPECL to LVDS with
Internal 100
W
Termination Resistor
1.50 V
2.5 V LVPECL
Output
LVDS
Input
Figure 7. Capacitive Coupling ECL to LVDS Using
V
OS
Reference Voltage
720 mV
0.78 V
Direct Interfacing
Interfacing from 2.5 V LVPECL to LVDS
Where R
T
= 75
W
Provided that the LVDS receiver can tolerate large input
voltage peak to peak amplitude, 2.5 V LVPECL can be
directly interfaced to LVDS receiver using proper ECL
termination. 2.5 V LVPECL will be able to drive LVDS
receiver with and without internal 100
W
termination
resistor. (See Figures 8, 9 and 10).
2.5 V
Z
O
V
CC
Figure 10. PSPICE Simulation Levels of 2.5V LVPECL
to LVDS Interface with Example Resistor Values
Furthermore, sreies termination can be used to reduce the
amplitude of the signal as described in AND8020
application note, by placing R
S
resistor between the driver
and the transmission line. (See Figures 11, 12 and 13).
2.5 V
R
S
Z
O
V
CC
LVPECL
Z
O
100
W
LVDS
LVPECL
R
S
Z
O
100
W
LVDS
R
T
R
T
R
T
R
T
Figure 8. Interfacing 2.5 V LVPECL to LVDS with
External 100
W
Termination Resistor
Figure 11. Interfacing 2.5 V LVPECL to LVDS with
Series R
S
and External 100
W
Termination Resistor
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