Low Skew, 1-to-12 LVCMOS / LVTTL
Clock Multiplier/Zero Delay Buffer
Data Sheet
87973
G
ENERAL
D
ESCRIPTION
The 87973 is a LVCMOS/LVTTL clock generator.
The 87973 has three selectable inputs and provides
fourteen LVCMOS/LVTTL outputs.
The 87973 is a highly flexible device. The three selectable in-
puts (1 differential and 2 single ended inputs) are often used in
systems requiring redundant clock sources. Up to three
different output frequencies can be generated among the three
output banks.
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. The output
frequency range is 8.33MHz to125MHz. The input frequency
range is 5MHz to 120MHz.
The 87973 also has a QSYNC output which can by used for
system synchronization purposes. It monitors Bank A and
Bank C outputs and goes low one period prior to coincident
rising edges of Bank A and Bank C clocks. QSYNC then goes
high again when the coincident rising edges of Bank A and
Bank C occur. This feature is used primarily in applications
where Bank A and Bank C are running at different frequencies,
and is particularly useful when they are running at non-integer
multiples of one another.
Example Applications:
1.
System Clock generator:
Use a 16.66MHz reference
clock to generate eight 33.33MHz copies for PCI and
four 100MHz copies for the CPU or PCI-X.
2.
Line Card Multiplier:
Multiply differential 62.5MHz from
a back plane to single-ended 125MHz for the line Card
ASICs and Gigabit Ethernet Serdes.
3.
Zero Delay buffer for Synchronous memory:
Fan out
up to twelve 100MHz copies from a memory controller
reference clock to the memory chips on a memory mod-
ule with zero delay.
F
EATURES
•
Fully integrated PLL
•
Fourteen LVCMOS/LVTTL outputs; twelve clock outputs,
one feedback, one sync
•
Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs
•
CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 8.33MHz to 125MHz
•
VCO range: 200MHz to 480MHz
•
Output skew: 550ps (maximum)
•
Cycle-to-cycle jitter: ±100ps (typical)
•
Full 3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free RoHS compliant package
•
Compatible with PowerPC™ and Pentium™ Microprocessors
P
IN
A
SSIGNMENT
©2015 Integrated Device Technology, Inc
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December 7, 2015
87973 Data Sheet
B
LOCK
D
IAGRAM
VCO_SEL
PLL_SEL
REF_SEL
CLK
nCLK
CLK0
CLK1
CLK_SEL
EXT_FB
0
1
PHASE
DETECTOR
LPF
VCO
1
0
0
1
D
Q
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
QA0
QA1
QA2
QA3
D
Q
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
QB0
QB1
QB2
QB3
FSEL_FB2
nMR/OE
POWER-ON
RESET
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
2
2
2
3
DATA GENERATOR
SYNC PULSE
0
÷2
1
D
Q
SYNC
FRZ
QC0
QC1
QC2
QC3
QFB
D
Q
SYNC
FRZ
SYNC
FRZ
FSEL_A0:1
FSEL_B0:1
FSEL_C0:1
FSEL_FB0:2
÷4, ÷6, ÷8, ÷10
D
Q
D
Q
SYNC
FRZ
QSYNC
FRZ_CLK
OUTPUT DISABLE
CIRCUITRY
12
FRZ_DATA
INV_CLK
©2015 Integrated Device Technology, Inc
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December 7, 2015
87973 Data Sheet
S
IMPLIFIED
B
LOCK
D
IAGRAM
nMR/OE
FSEL_A[0:1]
CLK
nCLK
CLK0
CLK1
CLK_SEL
REF_SEL
2
1
0
1
VCO R
ANGE
200MHz - 480MHz
0
÷2
0
1
÷1
1
0
PLL
FSEL_
A1 A0
0 0
0 1
1 0
1 1
QAx
÷4
÷6
÷8
÷12
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
QA0
QA1
QA2
QA3
EXT_FB
FSEL_B[0:1]
2
VCO_SEL
PLL_SEL
FSEL_
B1 B0
0 0
0 1
1 0
1 1
QBx
÷4
÷6
÷8
÷10
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
QB0
QB1
QB2
QB3
FSEL_C[0:1]
2
FSEL_
C1 C0
0 0
0 1
1 0
1 1
QCx
÷2
÷4
÷6
÷8
QC0
SYNC
FRZ
QC1
QC2
QC3
0
SYNC
FRZ
SYNC
FRZ
1
INV_CLK
FSEL_FB[0:2]
3
FSEL_
FB2 FB1 FB0 QFB
0
0
0
÷4
0
0
1
÷6
0
1
0
÷8
0
1
1 ÷10
1
0
0
÷8
1
0
1 ÷12
1
1
0 ÷16
1
1
1 ÷20
FRZ_CLK
FRZ_DATA
O
UTPUT
D
ISABLE
C
IRCUITRY
SYNC
FRZ
QFB
QSYNC
©2015 Integrated Device Technology, Inc
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December 7, 2015
87973 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5, 26, 27
Name
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
PLL_SEL
Power
Input
Input
Input
Input
Pullup
Pullup
Pullup
Pullup
Type
Description
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs. When
LOW, resets the outputs to tristate and resets output divide circuitry.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Configuration data input for freeze circuitry.
LVCMOS / LVTTL interface levels.
Select pins control Feedback Divide value.
LVCMOS / LVTTL interface levels.
Selects between the PLL and reference clocks as the input to the output
dividers. When HIGH, selects PLL. When LOW, bypasses the PLL. LVC-
MOS / LVTTL interface levels.
Selects between CLK0 or CLK1 and CLK, nCLK inputs.
When HIGH, selects CLK, nCLK. When LOW, selects CLK0 or CLK1.
LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 and CLK1 as phase detector
reference. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS
/ LVTTL interface levels.
Reference clock inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
6
Input
Pullup
7
REF_SEL
Input
Pullup
8
9, 10
11
12
13
14
15, 24, 30, 35,
39, 47, 51
16, 18,
21, 23
17, 22, 33,
37, 45, 49
19, 20
25
28
29
31
32, 34,
36, 38
40, 41
42, 43
44, 46,
48, 50
52
CLK_SEL
CLK0,CLK1
CLK
nCLK
V
DDA
INV_CLK
GNDO
QC3, QC2,
QC1, QC0
V
DDO
FSEL_C1,
FSEL_C0
QSYNC
V
DD
QFB
EXT_FB
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
VCO_SEL
Input
Input
Input
Input
Power
Input
Power
Output
Power
Input
Output
Power
Output
Input
Output
Input
Input
Output
Input
Pullup
Pullup
Pullup
Pullup/
Inverting differential clock input. V
DD
/2 default when left floating.
Pulldown
Analog supply pin.
Pullup
Inverted clock select for QC2 and QC3 outputs.
LVCMOS / LVTTL interface levels.
Power supply ground.
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins.
Pullup
Select pins for Bank C outputs. LVCMOS / LVTTL interface levels.
Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing
Diagrams. LVCMOS / LVTTL interface levels.
Core supply pins.
Feedback clock output. LVCMOS / LVTTL interface levels.
Pullup
Extended feedback. LVCMOS / LVTTL interface levels.
Bank B clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Pullup
Pullup
Select pins for Bank B outputs. LVCMOS / LVTTL interface levels.
Select pins for Bank A outputs. LVCMOS / LVTTL interface levels.
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1.
When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
©2015 Integrated Device Technology, Inc
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December 7, 2015
87973 Data Sheet
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP /
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup/Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
V
DD
, V
DDA
, V
DDO
= 3.465V
5
7
Test Conditions
Minimum
Typical
4
51
18
12
Maximum
Units
pF
kW
pF
W
T
ABLE
3A. O
UTPUT
B
ANK
C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
FSEL_A1
0
0
1
1
FSEL_A0
0
1
0
1
Outputs
QA
÷4
÷6
÷8
÷12
0
0
1
1
Inputs
FSEL_B1
FSEL_B0
0
1
0
1
Outputs
QB
÷4
÷6
÷8
÷10
0
0
1
1
Inputs
FSEL_C1
FSEL_C0
0
1
0
1
Outputs
QC
÷2
÷4
÷6
÷8
T
ABLE
3B. F
EEDBACK
C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
FSEL_FB2
0
0
0
0
1
1
1
1
FSEL_FB1
0
0
1
1
0
0
1
1
FSEL_FB0
0
1
0
1
0
1
0
1
Outputs
QFB
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
T
ABLE
3C. C
ONTROL
I
NPUT
S
ELECT
F
UNCTION
T
ABLE
Control Pin
VCO_SEL
REF_SEL
CLK_SEL
PLL_SEL
nMR/OE
INV_CLK
Logic 0
VCO/2
CLK0 or CLK1
CLK0
BYPASS PLL
Master Reset/Output Hi Z
Non-Inverted QC2, QC3
Logic 1
VCO
CLK, nCLK
CLK1
Enable PLL
Enable Outputs
Inverted QC2, QC3
©2015 Integrated Device Technology, Inc
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December 7, 2015
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