PHD110NQ03LT
N-channel TrenchMOS™ logic level FET
Rev. 01 — 16 June 2004
M3D300
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
1.2 Features
s
Logic level threshold
s
Low on-state resistance
s
Low gate charge
s
Surface mount package.
1.3 Applications
s
Control FET in DC-to-DC converters
s
Switched-mode power supplies.
1.4 Quick reference data
s
V
DS
≤
25 V
s
P
tot
≤
115 W
s
I
D
≤
75 A
s
R
DSon
≤
4.6 mΩ.
2. Pinning information
Table 1:
Pin
1
2
3
mb
Pinning - SOT428 (D-PAK), simplified outline and symbol
Description
gate (g)
drain (d)
source (s)
mounting base;
connected to drain (d)
2
1
Top view
3
MBK091
Simplified outline
[1]
Symbol
d
mb
g
mbb076
s
SOT428 (D-PAK)
[1]
It is not possible to make a connection to pin 2 of the SOT428 package.
Philips Semiconductors
PHD110NQ03LT
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2:
Ordering information
Package
Name
Description
Plastic single-ended surface mounted package; 3 leads; one lead cropped
Version
Type number
PHD110NQ03LT
D-PAK
SOT428
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
mb
= 25
°C
peak source (diode forward) current T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
unclamped inductive load; I
D
= 43 A;
t
p
= 0.25 ms; V
DD
≤
15 V; R
GS
= 50
Ω;
V
GS
= 10 V; starting T
j
= 25
°C
T
mb
= 25
°C;
V
GS
= 5 V;
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 5 V;
Figure 2
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
mb
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
175
°C
25
°C ≤
T
j
≤
175
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
-
Max
25
25
±20
75
65
240
115
+175
+175
75
240
185
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
9397 750 13468
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 16 June 2004
2 of 12
Philips Semiconductors
PHD110NQ03LT
N-channel TrenchMOS™ logic level FET
120
P
der
(%)
80
03aa16
120
Ider
(%)
80
03af09
40
40
0
0
50
100
150
T
mb
(
°
C)
200
0
0
50
100
150
200
Tmb (°C)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
103
ID
(A)
03af11
Limit RDSon = VDS / ID
tp = 10
µs
102
100 µs
1 ms
DC
10
10 ms
100 ms
1
1
10
VDS (V)
102
T
mb
= 25
°C;
I
DM
is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 13468
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 16 June 2004
3 of 12
Philips Semiconductors
PHD110NQ03LT
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4:
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Conditions
mounted on a printed-circuit
board; minimum footprint
Min
-
-
Typ
-
75
Max
1.3
-
Unit
K/W
K/W
thermal resistance from junction to mounting base
Figure 4
thermal resistance from junction to ambient
Symbol Parameter
5.1 Transient thermal impedance
10
Zth(j-mb)
(K/W)
1
03af10
δ
= 0.5
0.2
10-1
0.1
0.05
0.02
P
10-2
δ
=
tp
T
single pulse
10-3
10-5
tp
T
10-4
10-3
10-2
10-1
1
tp (s)
t
10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 13468
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 16 June 2004
4 of 12
Philips Semiconductors
PHD110NQ03LT
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°C
T
j
= 150
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 25 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 175
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±15
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 175
°C
V
GS
= 10 V; I
D
= 25 A;
Figure 7
and
8
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 25 A; V
GS
= 0 V;
Figure 12
reverse recovery time
recovered charge
I
S
= 10 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V
V
DD
= 15 V; I
D
= 12.5 A; V
GS
= 5 V;
R
G
= 5.6
Ω
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 11
I
D
= 50 A; V
DD
= 15 V; V
GS
= 5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
-
-
26.7
8.5
8.4
2200
725
290
18
70
75
70
0.85
43
40
-
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
-
5.3
8.3
3.9
6.2
11.2
4.6
mΩ
mΩ
mΩ
-
-
-
0.05
-
10
1
500
100
µA
µA
nA
1
0.5
-
1.5
-
-
2
-
2.2
V
V
V
25
22
-
-
-
-
V
V
Conditions
Min
Typ
Max
Unit
Source-drain diode
9397 750 13468
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 16 June 2004
5 of 12
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