BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty
transistor
Rev. 3 — 1 September 2015
Product data sheet
1. Product profile
1.1 General description
The BLD6G21L-50 and BLD6G21LS-50 incorporate a fully integrated Doherty solution
using Ampleon’s state of the art GEN6 LDMOS technology. This device is perfectly suited
for TD-SCDMA base station applications at frequencies from 2010 MHz to 2025 MHz. The
main and peak device, input splitter and output combiner are integrated in a single
package. This package consists of one gate and drain lead and two extra leads of which
one is used for biasing the peak amplifier and the other is not connected. It only requires
the proper input/output match and bias setting as with a normal class-AB transistor.
Table 1.
Typical performance
RF performance at T
h
= 25
C.
Mode of operation
TD-SCDMA
[1][2]
[1]
[2]
f
(MHz)
2010 to 2025
V
DS
(V)
28
P
L(AV)
(W)
8
G
p
(dB)
14.5
D
(%)
43
ACPR
(dBc)
24
P
L(3dB)
(W)
53
Test signal: 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF.
I
Dq
= 170 mA (main); V
GS(amp)peak
= 0 V.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features and benefits
Typical TD-SCDMA performance at frequencies from 2010 MHz to 2025 MHz:
Average output power = 8 W
Power gain = 14.5 dB
Efficiency = 43 %
Fully optimized integrated Doherty concept:
integrated asymmetrical power splitter at input
integrated power combiner
peak biasing down to 0 V
low junction temperature
high efficiency
100 % peak power tested for guaranteed output power capability
BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
Integrated ESD protection
Good pair match (main and peak on the same chip)
Independent control of main and peak bias
Internally matched for ease of use
Excellent ruggedness
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
High efficiency RF power amplifiers with digital pre-distortion for TD-SCDMA multi
carrier applications in the 2010 MHz to 2025 MHz range.
2. Pinning information
Table 2.
Pin
1
2
3
4
5
Pinning
Description
drain
gate + bias main
source
n.c.
bias peak
4
2
5
001aak920
Simplified outline
Graphic symbol
BLD6G21L-50 (SOT1130A)
1
[1]
1
2
3
3
5
BLD6G21LS-50 (SOT1130B)
1
2
3
4
5
drain
gate + bias main
source
n.c.
bias peak
001aak920
1
[1]
1
2
3
3
5
2
4
5
[1]
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Package
Name
BLD6G21L-50
-
BLD6G21LS-50 -
Description
flanged ceramic package; 2 mounting holes; 4 leads
earless flanged ceramic package; 4 leads
Version
SOT1130A
SOT1130B
Type number
BLD6G21L-50_BLD6G21LS-50#3
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 3 — 1 September 2015
2 of 15
BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
4. Block diagram
main
amplifier
RF-input/bias main
2
90°
90°
1
RF-output/V
DS
bias peak
5
peak
amplifier
001aak932
Fig 1.
Block diagram of BLD6G21L-50 and BLD6G21LS-50
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Valid for both main and peak device.
Symbol
V
DS
V
GS(amp)main
V
GS(amp)peak
I
D
T
stg
T
j
Parameter
drain-source voltage
main amplifier gate-source voltage
peak amplifier gate-source voltage
drain current
storage temperature
junction temperature
Conditions
Min
-
0.5
0.5
-
65
-
Max
65
+13
+13
10.2
+150
200
Unit
V
V
V
A
C
C
6. Thermal characteristics
Table 5.
Symbol
Thermal characteristics
Parameter
Conditions
T
case
= 80
C;
P
L
= 8 W
[1]
Typ
2.1
Unit
K/W
R
th(j-case)
thermal resistance from junction to case
[1]
When operated with a 6-carrier TD-SCDMA modulated signal with PAR = 10.8 dB at 0.01 % probability on
CCDF.
7. Characteristics
Table 6.
Characteristics
Valid for both main and peak device.
Symbol Parameter
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
V
GSq
I
DSS
I
DSX
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
Conditions
V
GS
= 0 V; I
D
= 0.62 mA
V
DS
= 10 V; I
D
= 31 mA
V
DS
= 28 V; I
D
= 170 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
Min
65
1.4
-
Typ
-
1.8
-
Max
-
2.4
1.4
-
Unit
V
V
V
A
A
1.55 2.05 2.55
4.95 5.5
BLD6G21L-50_BLD6G21LS-50#3
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 3 — 1 September 2015
3 of 15
BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
Table 6.
Characteristics
…continued
Valid for both main and peak device.
Symbol Parameter
I
GSS
g
fs
R
DS(on)
gate leakage current
forward transconductance
drain-source on-state resistance
Conditions
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 1.55 A
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 1.085 A
Min
-
1.4
-
Typ
-
2.2
Max
140
-
Unit
nA
S
0.52 0.736
8. Application information
Table 7.
Application information
Mode of operation: 6-carrier TD-SCDMA; PAR 10.8 dB at 0.01 % probability on CCDF;
f = 2017.5 MHz; RF performance at V
DS
= 28 V; I
Dq
= 170 mA; V
GS(amp)peak
= 0 V; T
case
= 25
C;
unless otherwise specified; in a production circuit.
Symbol
P
L(AV)
G
p
D
PAR
O
RL
in
ACPR
Parameter
average output power
power gain
drain efficiency
output peak-to-average ratio
input return loss
adjacent channel power ratio
P
L(AV)
= 8 W
P
L(AV)
= 8 W
P
L(AV)
= 8 W
P
L(AV)
= 8 W
P
L(AV)
= 8 W
Conditions
Min
-
13
39
-
8
-
Typ
8
14.5
43
9.4
23
24
Max
-
-
-
-
-
20
Unit
W
dB
%
dB
dB
dBc
Table 8.
Application information
Mode of operation: Pulsed CW;
= 10 %; t
p
= 100
s; RF performance at V
DS
= 28 V; I
Dq
= 170 mA;
V
GS(amp)peak
= 0 V; T
case
= 25
C; unless otherwise specified; in a production circuit.
Symbol
P
L(3dB)
Parameter
output power at 3 dB gain compression
Conditions
Min
46
Typ
53
Max
-
Unit
W
8.1 Ruggedness in Doherty operation
The BLD6G21L-50 and BLD6G21LS-50 are capable of withstanding a load mismatch
corresponding to VSWR = 10 : 1 through all phases under the following conditions:
V
DS
= 28 V; I
Dq
= 170 mA; P
L
= 8 W (TD-SCDMA); f = 2017.5 MHz.
8.2 Impedance information
Table 9.
Typical impedance
Measured Load Pull data; typical values unless otherwise specified.
f
MHz
1995
2010
2017.5
2025
2040
Z
S
3.5
12.3j
3.6
12.7j
3.6
12.7j
3.7
12.7j
4.0
12.9j
Z
L
6.7
6.1j
6.7
6.1j
6.7
5.7j
6.4
5.2j
5.7
4.8j
BLD6G21L-50_BLD6G21LS-50#3
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 3 — 1 September 2015
4 of 15
BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
drain
Z
L
gate
Z
S
001aaf059
Fig 2.
Definition of transistor impedance
8.3 Performance curves
Performance curves are measured in a BLD6G21L-50 application circuit.
8.3.1 CW pulsed
001aam428
001aam429
17
G
p
(dB)
15
60
η
D
(%)
40
13
(6)
(5)
(4)
(3)
(2)
(1)
(1)
(2)
(3)
(4)
(5)
(6)
20
11
30
35
40
45
P
L
(dBm)
50
0
30
35
40
45
P
L
(dBm)
50
V
DS
= 28 V; I
Dq
= 170 mA (main); T
case
= 25
C;
f = 2017.5 MHz;
= 10 %; t
p
= 100
s
on 1 ms period.
(1) V
GS(amp)peak
= 0 V
(2) V
GS(amp)peak
= 0.2 V
(3) V
GS(amp)peak
= 0.4 V
(4) V
GS(amp)peak
= 0.5 V
(5) V
GS(amp)peak
= 0.6 V
(6) V
GS(amp)peak
= 0.8 V
V
DS
= 28 V; I
Dq
= 170 mA (main); T
case
= 25
C;
f = 2017.5 MHz;
= 10 %; t
p
= 100
s
on 1 ms period.
(1) V
GS(amp)peak
= 0 V
(2) V
GS(amp)peak
= 0.2 V
(3) V
GS(amp)peak
= 0.4 V
(4) V
GS(amp)peak
= 0.5 V
(5) V
GS(amp)peak
= 0.6 V
(6) V
GS(amp)peak
= 0.8 V
Fig 3.
Power gain as a function of load power;
typical values
Fig 4.
Drain efficiency as a function of load power;
typical values
BLD6G21L-50_BLD6G21LS-50#3
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 3 — 1 September 2015
5 of 15
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