21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV3810/PI90LVR3810
High-Speed Differential
Line Receivers
Features
• Ten line receivers meet or exceed the requirements of the
ANSI TIA/EIA-644-1995 Standard
• Designed for signaling rates up to 660 Mbps
• 0V to 3V common-mode input voltage range
• Operates from a single 3.3V supply
• Typical propagation delay time: 2.6ns
• Output skew 100ps (typical)
• Part-to-part skew is less than 1ns
• PI90LVR3810
Set up time: typical 1ns
Max. clock to output: 1ns
• Integrated 110-ohm termination on PI90LVT386
• Low Voltage TTL (LVTTL) levels are 5V tolerant
• Open-circuit fail safe
• Flow-through pin out
• Packaging:
48-Pin Thin Shrink Small Output TSSOP (A)
Description
The PI90LVx3810 family consists of ten differential line receivers
with 3-state outputs that implement Low-Voltage Differential Sig-
naling (LVDS). The PI90LVR3810 has integrated edge-triggered
D-type flops. Any of the differential receivers will provide a valid
logical output state with a ±100mV differential input voltage within
the input common-mode voltage range that allows 0 to 3V of ground
potential difference between two LVDS nodes. The independent EN
pins can be used to place the outputs in either a normal logic state
(high or low logic levels) or a high-impedance state. In high-
impedance state, outputs neither load nor drive the bus lines.
The intended application of these devices, and their signaling
techniques, is for point-to-point baseband data transmission over
controlled impedance media of approximately 100-Ohms with a 100-
Ohm termination resistor. The transmission media may be printed
circuit board traces, backplanes, or cables. The PI90LV3810’s 10
receivers integrated into the same substrate allow precise timing
alignment. In addition, the PI90LVR3810's integrated registers
resynchronize the data to the system clock, for additional signal
deskew.
The integrated registers in the PI90LVR3810 are particularly suitable
for interfacing with LVDS drivers such as the PI90LV3811 over long
distances where signal-to-signal skew may be a problem. On the
positive transition of the differential clock (CLK±) input, the Q
outputs of the flip-flop take on the logic levels set up at the
differential data (RIN±) inputs.
Old data can be retained or new data can be entered while the
outputs are in the high-impedance state. The EN pins do not affect
the internal operation of the flip-flops.
PI90LV3810
PI90LVR3810 Truth Table
SET
0
1
R
OUT
Q=D
Q=1
1
PS8664
02/21/03
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LVR3810 Block Diagram
PI90LV3810 Block Diagram
2
PI90LVR3810 Pin Configuration
PI90LV3810 Pin Configuration
PI90LV3810/PI90LVR3810
High-Speed Differential Line Receivers
PS8664
02/21/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV3810/PI90LVR3810
High-Speed Differential Line Receivers
Absolute Maximum Ratings
Over Operating Free-Air Temperature
(unless otherwise noted)
†
Supply Voltage Range, V
DD(1) .......................................
–0.5V to 4V
Voltage Range :
Enables or R
OUT ...................................................
–0.5V to V
DD
+2V
R
IN+
or R
IN– ...........................................................................
–0.5V to 4V
Electrostatic Discharge
(2)
:
R
IN+
, R
IN–
, and GND .......................... Class 3, A: 10kV, B:700V
All Pins ................................................. Class 3, A: 8kV, B:600V
Storage Temperature Range ............................. –65°C to 150°C
Lead Temperature 1, 6mm (1/16 inch)
from case for 10 seconds .................................................... 260°C
†
Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated under
"Recommended Operating Conditions" is not implied.
Exposure to Absolute-Maximum-Rated conditions for extended
periods may affect device reliability.
Notes:
1. All voltage values, except differential I/O bus voltages, are
with respect to ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7
Function Table
Diffe re ntial Input
R
IN
±
V
ID
_
100mV
>
>
–100mV > V
ID
_
100mV
CLK±
LVR
only
Enable s
EN
H
Output
R
OUT
H
?
L
Z
H
R
OUT0
↑
H
H
_
V
ID
< 100mV
X
Open
X
X
L
H
H
↑
H or L
H = High level
L = Low level
X = Irrelevent
Z = High-impedance (off)
? = Indeterminate
↑=
Rising edge of clock
Recommended Operating Conditions
M in.
Supply Voltage, V
CC
High- Level Input Voltage, V
IH
Low- Level Input Voltage, V
IL
Magnitude of Differential Input Voltage
V
ID
Common- Mode input Voltage, V
IC
Operating free- air temperature, T
A
0.1
V
ID
2
3.0
2.0
0.8
0.6
2.4
–V
ID
2
V
CC
–0.8
–40
85
°C
V
Nom.
3.3
M ax.
3.6
Units
3
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02/21/03
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV3810/PI90LVR3810
High-Speed Differential Line Receivers
Electrical Characteristics Over Recommended Operating Conditions
(unless otherwise noted)
Symbol
V
ITH+
V
ITH-
V
OH
V
OL
I
CC
Parameter
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
Low-level output voltage
Supply current
I
OH
= -8mA
I
OL
= 8mA
Enabled, No load
Disabled
V
I
= 0V
V
I =
2.4V
V
CC =
0V, V
I =
2.4V
V
IH =
2V
V
IL
= 0.8V
V
O
= 0V
V
O
= 3.6V
V
ID
= 0.4 sin 2.5E09t V
5
10
±1
10
10
-1.2
-13
-3
12
± 20
mA
-100
2.4
3
0.2
22
0.4
40
3
-20
µA
Test Conditions
Min.
Typ.
(1)
Max.
100
Units
mV
V
mV
mA
I
I
I
I(OFF)
I
IH
I
IL
I
OZ
C
IN
Input current (R
IN
+ or R
IN
-inputs)
Power-off input current (R
IN
+ or R
IN
-inputs)
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
Input capacitance (R
IN
+ or R
IN
- inputs to GND
µA
pF
Note:
1. All typical values are at 25°C and with a 3.3V supply.
4
PS8664
02/21/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV3810/PI90LVR3810
High-Speed Differential Line Receivers
Switching Characteristics Over Recommended Operating Conditions
(unless otherwise noted)
Symbol
t
PLH
t
PHL
t
r
t
f
t
sk(p)
t
sk(o)
t
sk(pp)
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
Parame te r
Propagation delay time, low- to- high- level output
Propagation delay time, high- to- low- level output
Differential output signal rise time
Differential output signal fall time
Pulse skew (t
PHL
– t
PLH
)
Output skew
(2)
Part- to- part skew
(3)
Propagation delay time, high- impedance- to- high- level output
Propagation delay time, high- impedance- to- low- level output
Propagation delay time, high- level- to- high- impedance output
Propagation delay time, low- level- to- high- impedance output
Set- up time, data before CLK
↑
Hold- up time, data after CLK
↑
Pulse Duration, CLK HIGH or LOW
PI90LVR3810
1. 2
1. 0
1. 2
0.2
300
3.5
MHz
See Figure 3
(4)
7
15
ns
See Figure 2
(PI90LV3810)
Te s t Conditions
M in.
1
Typ.
(1)
2.6
2.5
800
150
100
M a x.
4
Units
ns
500
1400
600
450
1
ps
t
PLH,
t
PHL
Propagation delay time, CLK to R
OUT
f
MAX
Maximum Clock frequency
Notes:
1. All typical values are at 25°C and with a 3.3V supply
2. t
sk(o)
is the magnitude of the time difference between the t
PLH
or t
PHL
of all drivers of a single device with all of their inputs
connected together.
3. t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4. R
OUT0
disable time is 1 nanosecond greater.
5
PS8664
02/21/03
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