Burr Brown Products
from Texas Instruments
TLV320AIC32
SLAS479A – AUGUST 2005 – REVISED SEPTEMBER 2005
LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
FEATURES
•
Stereo Audio DAC
– 100 dB A Signal-to-Noise Ratio
– 16/20/24/32-Bit Data
– Supports Rates From 8 kHz to 96 kHz
– 3D/Bass/Treble/EQ/De-Emphasis Effects
Stereo Audio ADC
– 92 dB A Signal-to-Noise Ratio
– Supports Rates From 8 kHz to 96 kHz
Six Audio Input Pins
– Six Stereo Single-Ended Inputs
Six Audio Output Drivers
– Stereo 8-Ω, 500 mw/Channel Speaker Drive
Capability
– Stereo Fully-Differential or Single-Ended
Headphone Drivers
– Fully Differential Stereo Line Outputs
Low Power: 14-mW Stereo, 48-kHz Playback
With 3.3-V Analog Supply
Programmable Input/Output Analog Gains
Automatic Gain Control (AGC) for Record
Programmable Microphone Bias Level
Programmable PLL for Flexible Clock
Generation
I
2
C Control Bus
Audio Serial Data Bus Supports I
2
S,
Left/Right-Justified, DSP, and TDM Modes
Extensive Modular Power Control
Power Supplies:
– Analog: 2.7 V – 3.6 V
– Digital Core: 1.525 V – 1.95 V
– Digital I/O: 1.1 V – 3.6 V
Available Packages: 5
×
5 mm, 32-Pin QFN
DESCRIPTION
The TLV320AIC32 is a low-power stereo-audio codec
with a stereo headphone amplifier, as well as multiple
inputs and outputs, programmable in single-ended or
fully-differential
configurations.
Extensive
register-based power control is included, enabling
stereo 48-kHz DAC playback as low as 14 mW from
a 3.3-V analog supply, making it ideal for portable,
battery-powered audio and telephony applications.
The record path of the TLV320AIC32 contains
integrated microphone bias, digitally-controlled
stereo-microphone pre-amp, and automatic gain
control (AGC), with mix/mux capability among the
multiple analog inputs. The playback path includes
mix/mux capability from the stereo DAC and selected
inputs, through programmable volume controls, to the
various outputs.
The TLV320AIC32 contains four high-power output
drivers as well as two fully differential output drivers.
The high-power output drivers are capable of driving
a variety of load configurations, including up to four
channels of single-ended 16-Ω headphones using
ac-coupling capacitors, or stereo 16-Ω headphones in
a cap-less output configuration. In addition, pairs of
drivers can be used to drive 8-Ω speakers in a BTL
configuration at 500 mW per channel.
The stereo audio DAC supports sampling rates from
8 kHz to 96 kHz and includes programmable digital
filtering in the DAC path for 3D, bass, treble,
midrange effects, speaker equalization, and
de-emphasis for 32 kHz, 44.1 kHz, and 48 kHz rates.
The stereo-audio ADC supports sampling rates from
8 kHz to 96 kHz and is preceded by programmable
gain amplifiers providing up to +59.5 dB analog gain
for low-level microphone inputs.
The serial control bus supports the I
2
C protocol, while
the serial-audio data bus is programmable for I
2
S,
left/right justified, DSP, or TDM modes. A highly
programmable PLL is included for flexible clock
generation and support for all standard audio rates
from a wide range of available MCLKs, varying from
512 kHz to 50 MHz, with special attention paid to the
most popular cases of 12 MHz, 13 MHz, 16 MHz,
19.2 MHz, and 19.68 MHz system clocks.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TLV320AIC32
www.ti.com
SLAS479A – AUGUST 2005 – REVISED SEPTEMBER 2005
The TLV320AIC32 operates from an analog supply of
2.7 V – 3.6 V, a digital core supply of 1.525 V – 1.95
V, and a digital I/O supply of 1.1 V – 3.6 V. The
device is available in a 5
×
5 mm, 32-lead QFN
package.
SIMPLIFIED BLOCK DIAGRAM
AVSS_ADC
AVDD_DAC
AVSS_DAC
DRVDD
DRVSS
DRVDD
DVDD
DVSS
IOVDD
WCLK
DIN
DOUT
BCLK
+
HPL+
Voltage Supplies
Audio Serial
Bus
MIC2/LINE2L
VCM
MIC3/LINE3L
HPL-/HPLCOM
+
PGA
0/+59.5dB
0.5dB
steps
PGA
0/+59.5dB
0.5dB
steps
Volume Ctl
& Effects
DAC
L
MIC1/LINE1L
+
+
ADC
+
ADC
Volume Ctl
& Effects
DAC
R
VCM
MIC1/LINE1R
HPR-/HPRCOM/
SPKFC
MIC3/LINE3R
+
MIC2/LINE2R
2
I C Control
Bus
HPR+
Bias/
Reference
Audio Clock
Generation
+
LINE_OUT_L+
LINE_OUT_L-
+
LINE_OUT_R+
LINE_OUT_R-
MICBIAS
Figure 1. Simplified Codec Block Diagram
PACKAGE/ORDERING INFORMATION
PRODUCT
TLV320AIC32
PACKAGE
QFN-32
PACKAGE
DESIGNATOR
RHB
OPERATING
TEMPERATURE
RANGE
–40°C to 85°C
ORDERING NUMBER
TLV320AIC32IRHB
TLV320AIC32IRHBR
TRANSPORT
MEDIA, QUANTITY
Rails, 73
Tape and Reel, 3000
MCLK
SDA
SCL
RESETB
2
TLV320AIC32
www.ti.com
SLAS479A – AUGUST 2005 – REVISED SEPTEMBER 2005
DEVICE INFORMATION
PIN ASSIGNMENTS
1
8
32
9
25
24
16
17
TERMINAL FUNCTIONS
TERMINAL
NAME
MCLK
BCLK
WCLK
DIN
DOUT
DVSS
IOVDD
SCL
SDA
MIC1L/LINE1L
MIC1R/LINE1
R
MIC2L/LINE2L
MIC2R/LINE2
R
MIC3L/LINE3L
MICBIAS
MIC3R/LINE3
R
AVSS1
DRVDD
HPLOUT
HPLCOM
DRVSS
HPRCOM
HPROUT
DRVDD
AVDD
AVSS2
LEFT_LOP
LEFT_LOM
QFN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
I
I/O
I/O
I
O
I/O
I/O
I
I/O
I
I
I
I
I
O
I
I
O
O
O
O
O
O
O
I
I
O
O
Master clock input
Audio serial data bus bit clock input/output
Audio serial data bus word clock input/output
Audio serial data bus data input
Audio serial data bus data output
Digital core / I/O Ground Supply, 0 V
Digital I/O voltage supply, 1.1 V – 3.6 V
I2C serial clock input
I2C serial data input/output
Left input 1
Right input 1
Left input 2
Right input 2
Left input 3
Microphone bias voltage output
Right input 3
Analog ADC ground supply, 0 V
Analog ADC and output driver voltage supply, 2.7 V – 3.6 V
High power output driver (left +)
High power output driver (left - or multi-functional)
Analog output driver ground supply, 0 V
High power output driver (right - or multi-functional)
High power output driver (right +)
Analog output driver voltage supply, 2.7 V – 3.6 V
Analog DAC voltage supply, 2.7 V – 3.6 V
Analog DAC ground supply, 0 V
Left line output (+)
Left line output (-)
3
DESCRIPTION
TLV320AIC32
www.ti.com
SLAS479A – AUGUST 2005 – REVISED SEPTEMBER 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
RIGHT_LOP
RIGHT_LOM
RESET
DVDD
QFN NO.
29
30
31
32
I
I/O
O
O
Right lineo output (+)
Right line output (-)
Reset
Digital core voltage supply, 1.525 V – 1.95 V
DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
AVDD to AVSS1/2, DRVDD to DRVSS
AVDD to DRVSS
IOVDD to DVSS
DVDD to DVSS
AVDD to DRVDD
Digital input voltage to DVSS
Analog input voltage to AVSS1/2
Operating temperature range
Storage temperature range
T
J
Max
θ
JA
(1)
Junction temperature
Power dissipation
Thermal impedance
–0.3 to 3.9
–0.3 to 3.9
–0.3 to 3.9
–0.3 to 2.5
–0.1 to 0.1
–0.3 V to IOVDD+0.3
–0.3 V to AVDD+0.3
-40 to +85
-65 to +105
105
(T
J
Max – T
A
) /
θ
JA
44
°C/W
UNIT
V
V
V
V
V
V
V
°C
°C
°C
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
(1)
T
A
= 25°C
POWER RATING
1.82 W
(1)
DERATING FACTOR
22.7 mW/°C
T
A
= 75°C
POWER RATING
681 mW
T
A
= 85°C
POWER RATING
454 mW
This data was taken using 2 oz. trace and copper pad that is soldered directly to a JEDEC standard 4-layer 3 in
×
3 in PCB.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
AVDD,
Analog supply voltage
DRVDD1
/2
(1)
DVDD
(1)
V
I
Digital core supply voltage
Analog full-scale 0 dB input voltage (DRVDD1 = 3.3 V)
Stereo line-output load resistance
Stereo headphone-output load resistance
Digital output load capacitance
T
A
(1)
Operating free-air temperature
–40
10
16
10
85
IOVDD
(1)
Digital I/O supply voltage
2.7
NOM
3.3
MAX
3.6
UNIT
V
1.525
1.1
1.8
1.8
0.707
1.95
3.6
V
V
V
RMS
kΩ
Ω
pF
°C
Analog voltage values are with respect to AVSS1, AVSS2, DRVSS; digital voltage values are with respect to DVSS.
4
TLV320AIC32
www.ti.com
SLAS479A – AUGUST 2005 – REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER
AUDIO ADC
Input signal level (0-dB)
Signal-to-noise ratio,
A-weighted
(1) (2)
Dynamic range, A-weighted
(1) (2)
THD
Total harmonic distortion
Power supply rejection ratio
ADC channel separation
ADC gain error
ADC programmable gain
amplifier maximum gain
ADC programmable gain
amplifier step size
MIC1/LINE1 inputs, routed to single ADC
Input mix attenuation = 0 dB
MIC2/LINE2 inputs, input mix attenuation = 0 dB
MIC3/LINE3 inputs, input mix attenuation = 0 dB
Input resistance
MIC1/LINE1 inputs,
input mix attenuation = –12 dB
MIC2/LINE2 inputs,
input mix attenuation = –12 dB
MIC3/LINE3 inputs,
input mix attenuation = –12 dB
Input capacitance
Input level control minimum
attenuation setting
Input level control maximum
attenuation setting
Input level control attenuation
step size
ADC DIGITAL DECIMATION FILTER,
Filter gain from 0 to 0.39 Fs
Filter gain at 0.4125 Fs
Filter gain at 0.45 Fs
Filter gain at 0.5 Fs
Filter gain from 0.55 Fs to 64 Fs
Filter group delay
MICROPHONE BIAS
2.0
Bias voltage
Programmable settings, load = 750
Ω
2.25
2.5
AVDD-
0.2
(1)
(2)
Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
5
2.75
V
Fs = 48 kHz
±0.1
–0.25
–3
–17.5
–75
17/Fs
dB
dB
dB
dB
dB
Sec
MIC1/LINE1 inputs
Single-ended input
Fs = 48 kHz, 0 dB PGA gain, MIC1/LINE1 inputs
selected and AC-shorted to ground
Fs = 48 kHz, 1-kHz –60 dB full-scale input applied at
MIC1/LINE1 inputs, 0-dB PGA gain
Fs = 48 kHz, 1-kHz –2dB full-scale input applied at
MIC1/LINE1 inputs, 0-dB PGA gain
234 Hz, 100 mVpp on AVDD, DRVDD
1 kHz, –2 dB MIC3L to MIC3R
1 kHz, –2 dB MIC2L to MIC2R
1 kHz, –2 dB MIC1L to MIC1R
1 kHz input, 0 dB PGA gain
1-kHz input tone, R
SOURCE
< 50
Ω
80
0.707
92
92
–90
0.003%
46
–80
–99
–-73
0.7
59.5
0.5
20
20
20
80
80
80
10
0
12
1.5
pF
dB
dB
dB
kΩ
dB
dB
dB
dB
–75
0.017%
dB
V
RMS
dB
dB
dB
TEST CONDITIONS
MIN
TYP
MAX
UNIT
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