W24L011A
128K
×
8 HIGH SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L011A is a high speed, low power CMOS static RAM organized as 131072 x 8 bits that
operates on a single 3.3-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•
High speed access time: 10/12/15 nS
•
Single +3.3V power supply
•
Center power/ground pin configuration
•
Fully static operation
•
All inputs and outputs directly TTL compatible
•
Three-state outputs
•
Available packages: 32-pin 300 mil SOJ, Small
TSOP-I (8 x 13.4 mm), TSOP-I (8 x 20 mm)
and 400 mil SOJ
PIN CONFIGURATIONS
A0
A1
A2
A3
CS#
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE#
A4
A5
A6
A7
A16
A15
A14
A13
OE#
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A12
A11
A10
A9
A8
BLOCK DIAGRAM
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
A0
.
.
A16
DECODER
CORE
ARRAY
CS
OE
WE
CONTROL
DATA I/O
I/O1
.
.
I/O8
PIN DESCRIPTION
SYMBOL
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE#
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A12
A11
A10
A9
A8
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
A0
A1
A2
A4
CS#
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE#
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0
−
A16
I/O1
−
I/O8
CS
WE
OE
V
DD
V
SS
32-pin
TSOP
-1-
Publication Release Date: April 26, 2002
Revision A3
W24L011A
TRUTH TABLE
CS
H
L
L
L
OE
X
H
L
X
WE
X
H
H
L
MODE
Not Selected
Output Disable
Read
Write
I/O1
−
I/O8
High Z
High Z
Data Out
Data In
V
DD
CURRENT
I
SB
, I
SB1
I
DD
I
DD
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to V
SS
Potential
Input/Output to V
SS
Potential
Allowable Power Dissipation
Storage Temperature
Operating Temperature
RATING
-0.5 to +4.6
-0.5 to V
DD
+0.5
1.0
-65 to +150
0 to +70
UNIT
V
V
W
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(V
DD
= 3.3V
±5%,
V
SS
= 0V, T
A
= 0 to 70° C)
PARAMETER
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage
Current
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
SYM.
VI
L
VI
IH
I
LI
I
LO
V
OL
V
OH
I
DD
TEST CONDITIONS
-
-
VIN = V
SS
to V
DD
VI/O = V
SS
to V
DD
, CS = V
IH
(min.) or
OE = V
IH
(min.) or WE = V
IL
(max.)
I
OL
= +8.0 mA
I
OH
= -4.0 mA
CS = V
IL
(max.), I/O = 0 mA
Cycle = mim., Duty = 100%
10
12
15
MIN.
-0.5
+2.0
-10
TYP.
-
-
-
MAX.
0.8
V
DD
+0.5
+10
UNIT
V
V
µA
µA
V
V
-10
-
2.4
-
-
-
-
-
-
-
-
-
-
-
-
-
+10
0.4
-
130
120
100
15
5
mA
Standby Power
Supply Current
I
SB
I
SB
1
CS = V
IH
(min.)
CS
≥
V
DD
-0.2V
mA
mA
Note: Typical characteristics are at V
DD
= 3.3V, T
A
= 25° C.
-2-
W24L011A
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
C
IN
C
I/O
CONDITIONS
V
IN
= 0V
V
OUT
= 0V
MAX.
8
10
UNIT
pF
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
0V to 3V
3 nS
1.5V
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
CONDITIONS
AC Test Loads and Waveform
R1 320 ohm
R1 320 ohm
3.3V
OUTPUT
OUTPUT
30 pF
Including
Jig and
Scope
R2
350 ohm
5pF
Including
Jig and
Scope
R2
350 ohm
3.3V
(For T
CLZ,
T
OLZ,
T
CHZ,
T
OHZ,
T
WHZ,
T
OW
)
3.0V
90%
10%
3 nS
10%
90%
0V
3 nS
-3-
Publication Release Date: April 26, 2002
Revision A3
W24L011A
AC Characteristics, continued
(V
DD
= 3.3V
±5%,
V
SS
= 0V, T
A
= 0 to 70°)
Read Cycle
PARAMETER
SYM.
W24L011A-10
MIN.
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
T
RC
T
AA
T
ACS
T
AOE
T
CLZ
T
OLZ
*
T
CHZ
T
OHZ
*
T
OH
10
-
-
-
3
0
-
-
3
MAX.
-
10
10
5
-
-
5
5
-
W24L011A-12
MIN.
12
-
-
-
3
0
-
-
3
MAX.
-
12
12
6
-
-
6
6
-
W24L011A-15
MIN.
15
-
-
-
-
-
-
-
3
8
8
-
MAX.
-
15
15
8
3
nS
nS
nS
nS
nS
nS
nS
nS
nS
UNIT
*
These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER
SYM.
W24L011A-10
MIN.
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
CS , WE
T
WC
T
CW
T
AW
T
AS
T
WP
T
WR
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
10
9
9
0
9
0
5
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
5
5
-
W24L011A-12
MIN.
12
10
10
0
10
0
7
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
6
6
-
W24L011A-15
MIN.
15
12
12
0
12
0
9
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
8
8
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
UNIT
*
These parameters are sampled but not 100% tested.
-4-
W24L011A
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled,
CS
=
OE
= V
IL,
WE
= V
IH
)
T
RC
Address
T
AA
T
OH
T
OH
D
OUT
Read Cycle 2
(Chip Select Controlled)
T
RC
Address
CS
T
ACS
T
CLZ
D
OUT
T
CHZ
Read Cycle 3
(Output Enable Controlled)
T
RC
Address
T
AA
OE
T
AOE
T
OLZ
CS
T
ACS
T
CLZ
D
OUT
T
CHZ
T
OH
-5-
Publication Release Date: April 26, 2002
Revision A3
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