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W24L011AJ-10

Description
128K X 8 High Speed CMOS Static RAM
Categorystorage    storage   
File Size143KB,10 Pages
ManufacturerWinbond Electronics Corporation
Websitehttp://www.winbond.com.tw
Download Datasheet Parametric Compare View All

W24L011AJ-10 Overview

128K X 8 High Speed CMOS Static RAM

W24L011AJ-10 Parametric

Parameter NameAttribute value
Parts packaging codeSOJ
package instructionSOJ, SOJ32,.34
Contacts32
Reach Compliance Codeunknow
ECCN code3A991.B.2.B
Maximum access time10 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J32
length20.955 mm
memory density1048576 bi
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
power supply3.3 V
Certification statusNot Qualified
Maximum seat height3.556 mm
Maximum standby current0.005 A
Minimum standby current3.14 V
Maximum slew rate0.13 mA
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
width7.62 mm
Base Number Matches1
W24L011A
128K
×
8 HIGH SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L011A is a high speed, low power CMOS static RAM organized as 131072 x 8 bits that
operates on a single 3.3-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
High speed access time: 10/12/15 nS
Single +3.3V power supply
Center power/ground pin configuration
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Available packages: 32-pin 300 mil SOJ, Small
TSOP-I (8 x 13.4 mm), TSOP-I (8 x 20 mm)
and 400 mil SOJ
PIN CONFIGURATIONS
A0
A1
A2
A3
CS#
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE#
A4
A5
A6
A7
A16
A15
A14
A13
OE#
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A12
A11
A10
A9
A8
BLOCK DIAGRAM
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
A0
.
.
A16
DECODER
CORE
ARRAY
CS
OE
WE
CONTROL
DATA I/O
I/O1
.
.
I/O8
PIN DESCRIPTION
SYMBOL
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE#
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A12
A11
A10
A9
A8
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
A0
A1
A2
A4
CS#
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE#
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0
A16
I/O1
I/O8
CS
WE
OE
V
DD
V
SS
32-pin
TSOP
-1-
Publication Release Date: April 26, 2002
Revision A3

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