CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Operating Characteristics – RTC
Test Conditions: V
DD
= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
V
DD
V
BAT
I
DD1
PARAMETER
Main Power Supply
Battery Supply Voltage
Supply Current
V
DD
= 5V
V
DD
= 3V
I
DD2
I
DD3
I
BAT
I
BATLKG
I
LI
I
LO
V
TRIP
V
TRIPHYS
V
BATHYS
EVIN
V
IL
V
IH
Hysteresis
I
EVPU
EVIN Pullup Current
V
SUP
= 3V
-0.3
0.7 x V
DD
0.05 x V
DD
1.5
0.3 x V
DD
V
DD
+ 0.3
V
V
V
µA
6
Supply Current With I
2
C Active
Supply Current (Low Power Mode)
Battery Supply Current
Battery Input Leakage
Input Leakage Current on SCL
I/O Leakage Current on SDA
V
BAT
Mode Threshold
V
TRIP
Hysteresis
V
BAT
Hysteresis
1.6
10
10
V
DD
= 5V
V
DD
= 5V, LPMODE = 1
V
BAT
= 3V
V
DD
= 5.5V, V
BAT
= 1.8V
100
100
2.2
35
50
2.64
60
100
CONDITIONS
MIN
(Note 9)
2.7
1.8
2
1.2
40
1.4
400
TYP
(Note 5)
MAX
(Note 9)
5.5
5.5
6
4
120
5
950
100
UNITS NOTES
V
V
µA
µA
µA
µA
nA
nA
nA
nA
V
mV
mV
2, 3
2, 8
2
2, 3
IRQ/EVDET and F
OUT
V
OL
Output Low Voltage
V
DD
= 5V, I
OL
= 3mA
V
DD
= 2.7V, I
OL
= 1mA
I
LO
Output Leakage Current
V
DD
= 5.5V
V
OUT
= 5.5V
100
0.4
0.4
400
V
V
nA
Power-Down Timing
Test Conditions: V
DD
= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
V
DD SR-
PARAMETER
V
DD
Negative Slew rate
CONDITIONS
MIN
(Note 9)
TYP
(Note 5)
MAX
(Note 9)
10
UNITS
V/ms
NOTES
4
FN6316 Rev 1.00
July 15, 2010
Page 3 of 24
ISL1221
I
2
C Interface Specifications
Test Conditions: V
DD
= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
SYMBOL
V
IL
V
IH
Hysteresis
V
OL
Cpin
f
SCL
t
IN
t
AA
PARAMETER
SDA and SCL Input Buffer LOW
Voltage
SDA and SCL Input Buffer HIGH
Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 3mA
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL falLing Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Any pulse narrower than the max
spec is suppressed.
SCL falling edge crossing 30% of
V
DD
, until SDA exits the 30% to
70% of V
DD
window.
SDA crossing 70% of V
DD
during
a STOP condition, to SDA
crossing 70% of V
DD
during the
following START condition.
Measured at the 30% of V
DD
crossing.
Measured at the 70% of V
DD
crossing.
SCL rising edge to SDA falling
edge. Both crossing 70% of V
DD
.
From SDA falling edge crossing
30% of V
DD
to SCL falling edge
crossing 70% of V
DD
.
From SDA exiting the 30% to
70% of V
DD
window, to SCL
rising edge crossing 30% of V
DD.
From SCL falling edge crossing
30% of V
DD
to SDA entering the
30% to 70% of V
DD
window.
From SCL rising edge crossing
70% of V
DD
, to SDA rising edge
crossing 30% of V
DD
.
From SDA rising edge to SCL
falling edge. Both crossing 70%
of V
DD
.
From SCL falling edge crossing
30% of V
DD
, until SDA enters the
30% to 70% of V
DD
window.
From 30% to 70% of V
DD.
From 70% to 30% of V
DD.
Total on-chip and off-chip
1300
V
DD
= 5V, I
OL
= 3mA
T
A
= +25°C, f = 1MHz, V
DD
= 5V,
V
IN
= 0V, V
OUT
= 0V
TEST CONDITIONS
MIN
(Note 9)
-0.3
0.7 x V
DD
0.05 x V
DD
0.4
10
400
50
900
TYP (Note 5)
MAX
(Note 9)
0.3 x V
DD
V
DD
+ 0.3
UNITS NOTES
V
V
V
V
pF
kHz
ns
ns
t
BUF
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
1300
600
600
600
ns
ns
ns
ns
t
SU:DAT
Input Data Setup Time
100
ns
t
HD:DAT
Input Data Hold Time
0
900
ns
t
SU:STO
STOP Condition Setup Time
600
ns
t
HD:STO
STOP Condition Hold Time
600
ns
t
DH
Output Data Hold Time
0
ns
t
R
t
F
Cb
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
20 + 0.1 x Cb
20 +
0.1 x Cb
10
300
300
400
ns
ns
pF
7
7
7
FN6316 Rev 1.00
July 15, 2010
Page 4 of 24
ISL1221
I
2
C Interface Specifications
Test Conditions: V
DD
= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
(Continued)
SYMBOL
Rpu
PARAMETER
TEST CONDITIONS
MIN
(Note 9)
1
TYP (Note 5)
MAX
(Note 9)
UNITS NOTES
k
7
SDA and SCL Bus Pull-up Resistor Maximum is determined by t
R
Off-chip
and t
F
.
For Cb = 400pF, max is about
2~2.5k. For Cb = 40pF, max is
about 15~20k
NOTES:
2. IRQ and F
OUT
and EVDET Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. V
SUP
= V
DD
if in V
DD
Mode, V
SUP
= V
BAT
if in V
BAT
Mode.
7. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
8. A write to register 08h should only be done if V
DD
> V
BAT
, otherwise the device will be unable to communicate using I
2
C.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
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