74ABT821PW112 datasheet, PDF - EEWORLD Datasheet

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74ABT821PW112: DescriptionFlip Flops 10-BIT D-TYPE 3-S; Categorysemiconductor logic; File Size135KB，17 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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74ABT821PW112 Overview

Flip Flops 10-BIT D-TYPE 3-S

74ABT821PW112 Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	NXP
Product Category	Flip Flops
RoHS	Details
Number of Circuits	1
Logic Family	ABT
Logic Type	D-Type Edge Triggered Flip-Flop
Polarity	Non-Inverting
Input Type	Single-Ended
Output Type	Single-Ended
Propagation Delay Time	4.6 ns
High Level Output Current	- 32 mA
Low Level Output Current	64 mA
Supply Voltage - Min	4.5 V
Supply Voltage - Max	5.5 V
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	SOT-355
Packaging	Tube
Function	D-Type Bus Interface
Height	0.95 mm
Length	7.9 mm
Width	4.5 mm
Number of Channels	10
Number of Input Lines	10
Number of Output Lines	10
NumOfPackaging	1
Operating Supply Voltage	5 V
Factory Pack Quantity	1575
Unit Weight	0.000212 oz

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74ABT821

10-bit D-type flip-flop; positive-edge trigger; 3-state

Rev. 5 — 7 November 2011

Product data sheet

1. General description

The 74ABT821 high-performance BiCMOS device combines low static and dynamic

power dissipation with high speed and high output drive.

The 74ABT821 bus interface register is designed to eliminate the extra packages required

to buffer existing registers and provide extra data width for wider data/address paths of

buses carrying parity.

The 74ABT821 is a buffered 10-bit wide version of the 74ABT374A.

The 74ABT821 is a 10-bit, edge-triggered register coupled to ten 3-state output buffers.

The device is controlled by the clock (CP) and output enable (OE) control gates.

The register is fully edge triggered. The state of each D input, one set-up time before the

LOW-to-HIGH clock transition is transferred to the corresponding output Q of the flip-flop.

The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS

memories, or MOS microprocessors.

The active LOW output enable (OE) controls all ten 3-state buffers independent of the

When OE is HIGH, the outputs are in high-impedance OFF-state, which means they will

neither drive nor load the bus.

2. Features and benefits



High-speed parallel registers with positive-edge triggered D-type flip-flops



Ideal where high speed, light loading, or increased fan-in are required with MOS

microprocessors



Output capability: +64 mA and

32



Power-on 3-state



Power-on reset



Latch-up protection exceeds 500 mA per JESD78B class II level A



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V

74ABT821PW112 Related Products

	74ABT821PW112	74ABT821PW-T	74ABT821D623
Description	Flip Flops 10-BIT D-TYPE 3-S	Flip Flops 10-BIT D-TYPE 3-S	Flip Flops 10-BIT D-TYPE 3-S
Product Attribute	Attribute Value	-	Attribute Value
Manufacturer	NXP	-	NXP
Product Category	Flip Flops	-	Flip Flops
RoHS	Details	-	Details
Number of Circuits	1	-	1
Logic Family	ABT	-	ABT
Logic Type	D-Type Edge Triggered Flip-Flop	-	D-Type Edge Triggered Flip-Flop
Polarity	Non-Inverting	-	Non-Inverting
Input Type	Single-Ended	-	Single-Ended
Output Type	Single-Ended	-	Single-Ended
Propagation Delay Time	4.6 ns	-	4.6 ns
High Level Output Current	- 32 mA	-	- 32 mA
Low Level Output Current	64 mA	-	64 mA
Supply Voltage - Min	4.5 V	-	4.5 V
Supply Voltage - Max	5.5 V	-	5.5 V
Minimum Operating Temperature	- 40 C	-	- 40 C
Maximum Operating Temperature	+ 85 C	-	+ 85 C
Mounting Style	SMD/SMT	-	SMD/SMT
Package / Case	SOT-355	-	SOT-137
Packaging	Tube	-	Reel
Function	D-Type Bus Interface	-	D-Type Bus Interface
Height	0.95 mm	-	2.45 mm
Length	7.9 mm	-	15.6 mm
Width	4.5 mm	-	7.6 mm
Number of Channels	10	-	10
Number of Input Lines	10	-	10
Number of Output Lines	10	-	10
Operating Supply Voltage	5 V	-	5 V
Factory Pack Quantity	1575	-	1000

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