DSP56321VF240 datasheet, PDF - EEWORLD Datasheet

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DSP56321VF240: DescriptionDigital Signal Processors & Controllers - DSP, DSC 240Mhz/480MMACS 240Mhz EFCOP; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，84 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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Digital Signal Processors & Controllers - DSP, DSC 240Mhz/480MMACS 240Mhz EFCOP

DSP56321VF240 Parametric

Parameter Name	Attribute value
Brand Name	Freescale
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	NXP
Parts packaging code	BGA
package instruction	MOLDED ARRAY PROCESS, BGA-196
Contacts	196
Reach Compliance Code	not_compliant
ECCN code	3A991.A.2
Other features	ALSO REQUIRES 3.3V SUPPLY
Address bus width	18
barrel shifter	YES
bit size	24
boundary scan	YES
maximum clock frequency	240 MHz
External data bus width	24
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-PBGA-B196
JESD-609 code	e0
length	15 mm
low power mode	YES
Humidity sensitivity level	3
Number of terminals	196
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA196,14X14,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	220
power supply	1.6,3.3 V
Certification status	Not Qualified
RAM (number of words)	163840
Maximum seat height	1.6 mm
Maximum supply voltage	1.7 V
Minimum supply voltage	1.5 V
Nominal supply voltage	1.6 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead/Silver (Sn/Pb/Ag)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER

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Freescale Semiconductor

Technical Data

DSP56321

Rev. 11, 2/2005

DSP56321

24-Bit Digital Signal Processor

Memory Expansion Area

Program

RAM

32 K

24 bits

31 K

24 bits

and

Instruction

Cache

1024

24 bits

PM_EB

SCI

Triple

Timer

HI08

ESSI

EFCOP

X Data

RAM

80 K

24 bits

Y Data

RAM

80 K

24 bits

PIO_EB

XM_EB

Address

Generation

Unit

Six Channel

DMA Unit

Bootstrap

ROM

YAB

XAB

PAB

DAB

YM_EB

Peripheral

Expansion Area

External

Address

Bus

Switch

External

Bus

Interface

and

I - Cache

Control

External

Data

Bus

Switch

Power

Management

JTAG

OnCE™

Address

24-Bit

DSP56300

Core

DDB

YDB

XDB

PDB

GDB

Control

The DSP56321 is intended

for applications requiring a

large amount of internal

memory, such as networking

and wireless infrastructure

applications. The onboard

EFCOP can accelerate

general filtering applications,

such as echo-cancellation

applications, correlation, and

general-purpose convolution-

based algorithms.

Internal

Data

Bus

Switch

Data

What’s New?

Rev. 11 includes the following

changes:

•

Adds lead-free packaging and

part numbers.

Clock

PLL

Generator

EXTAL

XTAL

RESET

PINIT/NMI

Program

Interrupt

Controller

Program

Decode

Controller

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

Program

Address

Generator

Data ALU

24 + 56

→

56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

Figure 1.

DSP56321 Block Diagram

The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and

home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-

compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller

(see

Figure 1).

The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550

MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and

independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall

enhanced performance and signal quality with no impact on channel throughput or total channel support. This

device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.

Table of Contents

Data Sheet Conventions .......................................................................................................................................ii

Features...............................................................................................................................................................iii

Target Applications ............................................................................................................................................. iv

Product Documentation .......................................................................................................................................v

Chapter 1

Signals/Connections

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

1.10

1.11

Power ................................................................................................................................................................1-3

Ground ..............................................................................................................................................................1-3

Clock.................................................................................................................................................................1-3

External Memory Expansion Port (Port A) ......................................................................................................1-4

Interrupt and Mode Control ..............................................................................................................................1-6

Host Interface (HI08)........................................................................................................................................1-7

Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-10

Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-11

Serial Communication Interface (SCI) ...........................................................................................................1-12

Timers .............................................................................................................................................................1-13

JTAG and OnCE Interface ..............................................................................................................................1-14

Maximum Ratings.............................................................................................................................................2-1

Thermal Characteristics ....................................................................................................................................2-2

DC Electrical Characteristics............................................................................................................................2-2

AC Electrical Characteristics............................................................................................................................2-3

Package Description .........................................................................................................................................3-2

MAP-BGA Package Mechanical Drawing .....................................................................................................3-10

Thermal Design Considerations........................................................................................................................4-1

Electrical Design Considerations......................................................................................................................4-2

Power Consumption Considerations.................................................................................................................4-3

Input (EXTAL) Jitter Requirements .................................................................................................................4-4

Chapter 2

Specifications

2.1

2.2

2.3

2.4

Chapter 3

Packaging

3.1

3.2

Chapter 4

Design Considerations

4.1

4.2

4.3

4.4

Appendix A

Power Consumption Benchmark

Data Sheet Conventions

OVERBAR

“asserted”

“deasserted”

Examples:

Indicates a signal that is active when pulled low (For example, the

RESET

pin is active when

low.)

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Signal/Symbol

Logic State

Voltage

Signal State

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Note:

Values for

, and

are defined by individual product specifications.

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor

Features

Table 1

lists the features of the DSP56321 device.

Table 1.

DSP56321 Features

Feature

Description

• 275 million multiply-accumulates per second (MMACS) (550 MMACS using the EFCOP in filtering

applications) with a 275 MHz clock at 1.6 V core and 3.3 V I/O

• Object code compatible with the DSP56000 core with highly parallel instruction set

• Data arithmetic logic unit (Data ALU) with fully pipelined 24

24-bit parallel Multiplier-Accumulator (MAC),

56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional

ALU instructions, and 24-bit or 16-bit arithmetic support under software control

• Program control unit (PCU) with position independent code (PIC) support, addressing modes optimized for

DSP applications (including immediate offsets), internal instruction cache controller, internal memory-

expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-

, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and

triggering from interrupt lines and all peripherals

• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock

with skew elimination

• Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG)

test access port (TAP)

• Internal 24

24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core

• Operation at the same frequency as the core (up to 275 MHz)

• Support for a variety of filter modes, some of which are optimized for cellular base station applications:

• Real finite impulse response (FIR) with real taps

• Complex FIR with complex taps

• Complex FIR generating pure real or pure imaginary outputs alternately

• A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16

• Direct form 1 (DFI) Infinite Impulse Response (IIR) filter

• Direct form 2 (DFII) IIR filter

• Four scaling factors (1, 4, 8, 16) for IIR output

• Adaptive FIR filter with true least mean square (LMS) coefficient updates

• Adaptive FIR filter with delayed LMS coefficient updates

• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides

glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs

• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows

six-channel home theater)

• Serial communications interface (SCI) with baud rate generator

• Triple timer module

• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are

enabled

High-Performance

DSP56300 Core

Enhanced Filter

Coprocessor (EFCOP)

Internal Peripherals

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor

iii

DSP56321VF240 Related Products

	DSP56321VF240	DSP56321VF220	DSP56321VL275	DSP56321VL240	DSP56321VL220	DSP56321VF275
Description	Digital Signal Processors & Controllers - DSP, DSC 240Mhz/480MMACS 240Mhz EFCOP	Digital Signal Processors & Controllers - DSP, DSC 220Mhz/440MMACS 220Mhz EFCOP	Digital Signal Processors & Controllers - DSP, DSC 24 BIT DSP PBFREE	Digital Signal Processors & Controllers - DSP, DSC 24 BIT DSP PBFREE	Digital Signal Processors & Controllers - DSP, DSC 24 BIT DSP PBFREE	Digital Signal Processors & Controllers - DSP, DSC 275Mhz/550MMACS 275Mhz EFCOP
Is it lead-free?	Contains lead	Contains lead	Lead free	Lead free	Lead free	Contains lead
Is it Rohs certified?	incompatible	incompatible	conform to	conform to	conform to	incompatible
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	MOLDED ARRAY PROCESS, BGA-196	MOLDED ARRAY PROCESS, BGA-196	LEAD FREE, MOLDED ARRAY PROCESS, BGA-196	LEAD FREE, MOLDED ARRAY PROCESS, BGA-196	LEAD FREE, MOLDED ARRAY PROCESS, BGA-196	MOLDED ARRAY PROCESS, BGA-196
Contacts	196	196	196	196	196	196
Reach Compliance Code	not_compliant	not_compliant	unknown	unknown	unknown	not_compliant
ECCN code	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2
Other features	ALSO REQUIRES 3.3V SUPPLY	ALSO REQUIRES 3.3V SUPPLY	ALSO REQUIRES 3.3V SUPPLY	ALSO REQUIRES 3.3V SUPPLY	ALSO REQUIRES 3.3V SUPPLY	ALSO REQUIRES 3.3V SUPPLY
Address bus width	18	18	18	18	18	18
barrel shifter	YES	YES	YES	YES	YES	YES
bit size	24	24	24	24	24	24
boundary scan	YES	YES	YES	YES	YES	YES
maximum clock frequency	240 MHz	220 MHz	275 MHz	240 MHz	220 MHz	275 MHz
External data bus width	24	24	24	24	24	24
Format	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-PBGA-B196	S-PBGA-B196	S-PBGA-B196	S-PBGA-B196	S-PBGA-B196	S-PBGA-B196
JESD-609 code	e0	e0	e1	e1	e1	e0
length	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm
low power mode	YES	YES	YES	YES	YES	YES
Humidity sensitivity level	3	3	3	3	3	3
Number of terminals	196	196	196	196	196	196
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA
Encapsulate equivalent code	BGA196,14X14,40	BGA196,14X14,40	BGA196,14X14,40	BGA196,14X14,40	BGA196,14X14,40	BGA196,14X14,40
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	220	220	260	260	260	260
power supply	1.6,3.3 V	1.6,3.3 V	1.6,3.3 V	1.6,3.3 V	1.6,3.3 V	1.6,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
RAM (number of words)	163840	163840	163840	163840	163840	163840
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Minimum supply voltage	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
Nominal supply voltage	1.6 V	1.6 V	1.6 V	1.6 V	1.6 V	1.6 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal surface	Tin/Lead/Silver (Sn/Pb/Ag)	Tin/Lead/Silver (Sn/Pb/Ag)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead/Silver (Sn/Pb/Ag)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	40	40	40	40
width	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER
Brand Name	Freescale	Freescale	Freescale	-	-	Freescale
Base Number Matches	-	-	1	1	1	1

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