CM2009
VGA Port Companion Circuit
Features
•
•
Includes ESD protection, level-shifting, buffering
and sync impedance matching
7 channels of ESD protection for all VGA port con-
nector pins meeting IEC-61000-4-2 Level 4 ESD
requirements (
±
8kV contact discharge)
Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF maximum
5V drivers for HSYNC and VSYNC lines
Integrated impedance matching resistors on sync
lines
Bi-directional level shifting N-channel FETs pro-
vided for DDC_CLK & DDC_DATA channels
Backdrive protection on DDC lines
Compact 16-lead QSOP package
Product Description
The CM2009 connects between a video graphics con-
troller embedded in a PC, graphics adapter card or set
top box and the VGA or DVI-I port connector. The
CM2009 incorporates ESD protection for all signals,
level shifting for the DDC signals and buffering for the
SYNC signals. ESD protection for the video, DDC and
SYNC lines is implemented with low-capacitance cur-
rent steering diodes.
All ESD diodes are designed to safely handle the high
current spikes specified by IEC-61000-4-2 Level 4
(±8KV contact discharge if C
BYP
is present,
±4KV
if
not). The ESD protection for the DDC signal pins are
designed to prevent "back current" when the device is
powered down while connected to a monitor that is
powered up.
Separate positive supply rails are provided for the
VIDEO, DDC and SYNC channels to facilitate interfac-
ing with low voltage video controller ICs to provide
design flexibility in multi-supply-voltage environments.
(cont’d
next page)
•
•
•
•
•
•
Applications
•
VGA and DVI-I ports in:
- Desktop and Notebook PCs
- Graphics Cards
- Set Top Boxes
Simplified Electrical Schematic
9
V
CC_VIDEO
2
12
DDC_OUT1
DDC_OUT2
V
CC_DDC
7
BYP
8
V
CC_SYNC
1
VIDEO_1
VIDEO_2
VIDEO_3
3
4
5
R
T
R
T
GND
6
16
14
DDC_IN1
DDC_IN2
SYNC_IN1
SYNC_IN2
10
11
13
15
GND
SYNC_OUT2
SYNC_OUT1
©
2004 California Micro Devices Corp. All rights reserved.
08/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
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www.calmicro.com
1
CM2009
Product Description (cont’d)
Two non-inverting drivers provide buffering for the
HSYNC and VSYNC signals from the video controller
IC (SYNC1, SYNC2). These buffers accept TTL input
levels and convert them to CMOS output levels that
swing between Ground and V
CC_SYNC
, which is typi-
cally 5V. Additionally, each driver has a series termina-
tion resistor (R
T
) connected to the SYNC_OUT pin,
eliminating the external termination resistors typically
required for the HSYNC and VSYNC lines of the video
cable. There are three versions with different values of
R
T
to allow termination at typically 65
Ω
(CM2009-00)
or 55
Ω
(CM2009-01) or 15
Ω
(CM2009-02).
The 15Ω (CM2009-02) version will typically require two
external resistors which can be chosen to exactly
match the characteristic impedance of the SYNC lines
of the video cable.
Two N-channel MOSFETs provide the level shifting
function required when the DDC controller is operated
at a lower supply voltage than the monitor. The gate
terminals for these MOSFETS (V
CC_DDC
) should be
connected to the supply rail (typically 3.3V) that sup-
plies power to the transceivers of the DDC controller.
PACKAGE / PINOUT DIAGRAM
Top View
V
CC_SYNC
V
CC_VIDEO
VIDEO_1
VIDEO_2
VIDEO_3
GND
V
CC_DDC
BYP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_OUT2
DDC_IN2
DDC_IN1
DDC_OUT1
16 Pin QSOP
Note: This drawing is not to scale.
Ordering Information
PART NUMBERING INFORMATION
Standard Finish
R
OUT
65Ω
55Ω
15Ω
Pins
16
16
16
Package
QSOP
QSOP
QSOP
Ordering Part
Number
1
CM2009-00QS
CM2009-01QS
CM2009-02QS
Part Marking
CM2009-00QS
CM2009-01QS
CM2009-02QS
Lead-free Finish
Ordering Part
Number
1
CM2009-00QR
CM2009-01QR
CM2009-02QR
Part Marking
CM2009-00QR
CM2009-01QR
CM2009-02QR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
©
2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
08/12/04
CM2009
Pin Description
PIN DESCRIPTIONS
LEAD(s)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
V
CC_SYNC
V
CC_VIDEO
VIDEO_1
VIDEO_2
VIDEO_3
GND
V
CC_DDC
BYP
DDC_OUT1
DDC_IN1
DDC_IN2
DDC_OUT2
SYNC_IN1
SYNC_OUT1
SYNC_IN2
SYNC_OUT2
DESCRIPTION
This is an isolated supply input for the SYNC_1 and SYNC_2 level shifters and their associ-
ated ESD protection circuits.
This is a supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection cir-
cuits.
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the VGA controller device and the video connector.
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the VGA controller device and the video connector.
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the VGA controller device and the video connector.
Ground reference supply pin.
This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates.
This input is used to connect an external 0.2uF bypass capacitor to the DDC circuits, resulting
in an increased ESD withstand voltage rating for these circuits (±8kV with vs.
±4kV
without).
DDC signal output. Connects to the video connector side of one of the sync lines.
DDC signal input. Connects to the VGA controller side of one of the sync lines.
DDC signal input. Connects to the VGA controller side of one of the sync lines.
DDC signal output. Connects to the video connector side of one of the sync lines.
Sync signal buffer input. Connects to the VGA controller side of one of the sync lines.
Sync signal buffer output. Connects to the video connector side of one of the sync lines.
Sync signal buffer input. Connects to the VGA controller side of one of the sync lines.
Sync signal buffer output. Connects to the video connector side of one of the sync lines.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
V
CC_VIDEO
,V
CC_DDC
and V
CC_SYNC
Supply Voltage Inputs
ESD Diode Forward Current (one diode conducting at a time)
DC Voltage at Inputs
VIDEO_1, VIDEO_2, VIDEO_3
DDC_IN1, DDC_IN2
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2
Operating Temperature Range
Storage Temperature Range
Package Power Rating (T
A
=25°C)
RATING
[GND - 0.5] to +6.0
10
[GND - 0.5] to [V
CC_VIDEO
+ 0.5]
[GND - 0.5] to 6.0
[GND - 0.5] to 6.0
[GND - 0.5] to [V
CC_SYNC
+ 0.5]
-40 to +85
-40 to +150
500
UNITS
V
mA
V
V
V
V
°C
°C
mW
©
2004 California Micro Devices Corp. All rights reserved.
08/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
3
CM2009
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
PARAMETER
CONDITIONS
V
CC_VIDEO
= 5.0V; VIDEO inputs at V
CC_VIDEO
or GND
V
CC_DDC
= 5.0V
V
CC_SYNC
= 5V; SYNC inputs at GND or V
CC_SYNC
;
SYNC outputs unloaded
V
CC_SYNC
= 5V; SYNC inputs at 3.0V;
SYNC outputs unloaded
V
F
V
IH
V
IL
V
OH
V
OL
R
OUT
R
OUT
R
OUT
V
OH-02
V
OL-02
I
IN
ESD Diode Forward Voltage
Logic High Input Voltage
Logic Low Input Voltage
Logic High Output Voltage
Logic Low Output Voltage
SYNC Driver Output Resistance
(CM2009-00 only)
SYNC Driver Output Resistance
(CM2009-01 only)
SYNC Driver Output Resistance
(CM2009-02 only)
Logic High Output Voltage
(CM2009-02 only)
Input Current
VIDEO Inputs
SYNC_IN1, SYNC_IN2 Inputs
I
OFF
V
ON
C
IN_VID
t
PLH
t
PHL
t
R,
t
F
V
ESD
Level Shifting N-MOSFET "OFF" State
Leakage Current
Voltage Drop Across Level-shifting
N-MOSFET when "ON"
VIDEO Input Capacitance
SYNC Driver L => H Propagation Delay
SYNC Driver H => L Propagation Delay
SYNC Driver Output Rise & Fall Times
ESD Withstand Voltage
I
F
= 10mA
V
CC_SYNC
= 5.0V; Note 2
V
CC_SYNC
= 5.0V; Note 2
I
OH
= 0mA, V
CC_SYNC
= 5.0V; Note 2
I
OL
= 0mA, V
CC_SYNC
= 5.0V; Note 2
V
CC_SYNC
= 5.0V; SYNC Inputs at GND or 3.0V
V
CC_SYNC
= 5.0V; SYNC Inputs at GND or 3.0V
V
CC_SYNC
= 5.0V; SYNC Inputs at GND or 3.0V;
Note 5
I
OH
= 24mA; V
CC_SYNC
= 5.0V; Note 2
2.0
0.8
±1
±1
10
10
0.18
4
4.5
12
12
4
±8
65
55
15
4.85
0.15
2.0
0.6
MIN
TYP
MAX UNITS
10
10
50
2.0
1.0
µA
µA
µA
mA
V
V
V
V
V
Ω
Ω
Ω
V
V
µA
µA
µA
µA
V
pF
pF
ns
ns
ns
kV
I
CC_VIDEO
V
CC_VIDEO
Supply Current
I
CC_DDC
I
CC_SYNC
V
CC_DDC
Supply Current
V
CC_SYNC
Supply Current
Logic Low Output Voltage (CM2009-02 only) I
OL
= 24mA; V
CC_SYNC
= 5.0V; Note 2
V
CC_VIDEO
= 5.0V; V
IN
= V
CC_VIDEO
or GND
V
CC_SYNC
= 5.0V; V
IN
= V
CC_SYNC
or GND
(V
CC_DDC
- V
DDC_IN
)
≤
0.4V; V
DDC_OUT
= V
CC_DDC
(V
CC_DDC
- V
DDC_OUT
)
≤
0.4V; V
DDC_IN
= V
CC_DDC
V
CC_DDC
= 2.5V; V
S
= GND; I
DS
= 3mA;
V
CC_VIDEO
= 5.0V; V
IN
= 2.5V;
ƒ
= 1MHz; Note 4
V
CC_VIDEO
= 2.5V; V
IN
= 1.25V;
ƒ
= 1MHz; Note 4
C
L
= 50pF; V
CC
= 5.0V; Input t
R
and t
F
≤
5ns
C
L
= 50pF; V
CC
= 5.0V; Input t
R
and t
F
≤
5ns
C
L
= 50pF; V
CC
= 5.0V; Input t
R
and t
F
≤
5ns
V
CC_VIDEO
= V
CC_SYNC
= 5V; Notes 3, 4 & 5
Note 1: All parameters specified over standard operating conditions unless otherwise noted.
Note 2: These parameters apply only to the SYNC drivers. Note that R
OUT
= R
T
+ R
BUFFER
.
Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. BYP, V
CC_VIDEO
and V
CC_SYNC
must
be bypassed to GND via a low impedance ground plane with a 0.2µF, low inductance, chip ceramic capacitor at each supply
pin. ESD pulse is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to
GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1 and DDC_OUT2. All
other pins are ESD protected to the industry standard
±2kV
Human Body Model (MIL-STD-883, Method 3015). The bypass
capacitor at the BYP pin may optionally be omitted, in which case the max. ESD withstand voltage for the DDC_OUT1 and
DDC_OUT2 pins is reduced to
±4kV.
Note 4: This parameter is guaranteed by design and characterization.
Note 5: The SYNC_OUT pins on the CM2009-02 are guaranteed for 2kV HBM ESD protection.
©
2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
08/12/04
CM2009
Application Information
HSYNC
VSYNC
R1
100k
R2
100k
VCC_5V
VCCA_DAC
C2
0.2uF
C1
0.2uF
V
CC_SYNC
V
CC_VIDEO
SYNC_OUT2
C11
FB4
VSYNC_OUT
C12
SYNC_IN2
SYNC_OUT1
C9
FB3
C10
SYNC_GND
HSYNC_OUT
SYNC_IN1
DDC_OUT2
RED
GREEN
BLUE
75
75
75
VF**
VF**
VF**
C7
FB2
C8
DDC_DATA
DIG_GND
DDC_CLK
DDC_IN2
DDC_IN1
DDC_OUT1
C5
FB1
C6
CM2009
Optional EMI Filters
VIDEO_1
VIDEO_2
VIDEO_3
** VIDEO Filters.
See Note 4
RED_VIDEO
GREEN_VIDEO
BLUE_VIDEO
RED_GND
GREEN_GND
BLUE_GND
VCCGPIO
V
CC_DDC
DDCA_CLK
DDCA_DATA
Video Port
Connector
Figure 1. Typical Application Connection Diagram
NOTES
1 The CM2009 should be placed as close to the VGA or DVI-I connector as possible.
2 The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B signals.
3 If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with external 37.5
resistors.
4 "VF" are external video filters for the RGB signals.
5 Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins. Connections to
the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5mm) for best ESD
protection.
6 The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum ESD
withstand voltage at the DDC_OUT pins from
±8kV
to
±4kV.
If 8kV ESD protection is required, a 0.2µF ceramic bypass
capacitor should be connected between BYP and ground.
7 The SYNC buffers may be used interchangeably between HSYNC and VSYNC.
8 The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference only.
The component values and filter configuration may be changed to suit the application.
9 The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA.
10 R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when no moni-
tor is connected to the VGA connector. If used, it should be noted that "back current" may flow between the DDC pins and
VCC_5V via these resistors when VCC_5V is powered down.
11 For optimal ESD performance with the CM2009-02, an additional clamp device (such as the CMD PACDN042) should be
placed on HSYNC/VSYNC lines between the external matching resistor and the VGA connector.
©
2004 California Micro Devices Corp. All rights reserved.
08/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
5
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