S26KS512SDGBHB030 datasheet, PDF

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S26KS512SDGBHB030: DescriptionNOR Flash NOR; Categorystorage; File Size2MB，96 Pages; ManufacturerCypress Semiconductor

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S26KS512SDGBHB030 Overview

NOR Flash NOR

S26KS512SDGBHB030 Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Cypress Semiconductor
Product Category	NOR Flash
RoHS	Details
Packaging	Tray
Memory Type	NOR
Factory Pack Quantity	1

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S26KL512S/S26KS512S

S26KL256S/S26KS256S

S26KL128S/S26KS128S

512 Mbit (64 Mbyte)/256 Mbit (32 Mbyte)/

128 Mbit (16 Mbyte), 1.8V/3.0V

HyperFlash™ Family

Features



3.0V I/O, 11 bus signals

– Single ended clock



1.8V I/O, 12 bus signals

– Differential clock (CK, CK#)



Chip Select (CS#)



8-bit data bus (DQ[7:0])



Read-Write Data Strobe (RWDS)

– HyperFlash™ memories use RWDS only as a Read Data

Strobe



Up to 333 MB/s sustained read throughput



Double-Data Rate (DDR) – two data transfers per clock



166-MHz clock rate (333 MB/s) at 1.8V V



100-MHz clock rate (200 MB/s) at 3.0V V



96-ns initial random read access time

– Initial random access read latency: 5 to 16 clock cycles



Sequential burst transactions



Configurable Burst Characteristics

– Wrapped burst lengths:

– 16 bytes (8 clocks)

– 32 bytes (16 clocks)

– 64 bytes (32 clocks)

– Linear burst

– Hybrid option — one wrapped burst followed by linear burst

– Wrapped or linear burst type selected in each transaction

– Configurable output drive strength



Low Power Modes

– Active Clock Stop During Read: 12 mA, no wake-up

required

– Standby: 25 µA (typical), no wake-up required

– Deep Power-Down: 8 µA (typical)

– 300 µs wake-up required



INT# output to generate external interrupt

– Busy to Ready Transition

– ECC detection



RSTO# output to generate system level power-on reset

– User configurable RSTO# Low period



512-byte Program Buffer



Sector Erase

– Uniform 256-kB sectors

– Optional Eight 4-kB Parameter Sectors (32 kB total)



Advanced Sector Protection

– Volatile and non-volatile protection methods for each

sector



Separate 1024-byte one-time program array



Operating Temperature

– Industrial (–40°C to +85°C)

– Industrial Plus (–40°C to +105°C)

– Extended (–40°C to +125°C)

– Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)

– Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)

– Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)



ISO/TS16949 and AEC Q100 Certified



Endurance

– 100,000 program/erase cycles



Retention

– 20 year data retention



Erase and Program Current

– Max Peak



100 mA



Packaging Options

– 24-Ball FBGA



Additional Features

– ECC 1-bit correction, 2-bit detection

– CRC (Check-value Calculation)

Cypress Semiconductor Corporation

Document Number: 001-99198 Rev. *J

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised August 28, 2017

S26KL512S/S26KS512S

S26KL256S/S26KS256S

S26KL128S/S26KS128S

General Description



The Cypress HyperFlash family of products are high-speed CMOS, MirrorBit



NOR flash devices with the HyperBus low signal

count DDR (Double Data Rate) interface, that achieves high speed read throughput. The DDR protocol transfers two data bytes per

clock cycle on the data (DQ) signals. A read or write access for the HyperFlash consists of a series of 16-bit wide, one clock cycle

data transfers at the internal HyperFlash core and two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ

signals.

Both data and command/address information are transferred in DDR fashion over the 8-bit data bus. The clock input signals are

used for signal capture by the HyperFlash device when receiving command/address/data information on the DQ signals. The Read

Data Strobe (RWDS) is an output from the HyperFlash device that indicates when data is being transferred from the memory to the

host. RWDS is referenced to the rising and falling edges of CK during the data transfer portion of read operations.

Command/address/write-data values are center aligned with the clock edges and read-data values are edge aligned with the

transitions of RWDS.

Read and write operations to the HyperFlash device are burst oriented. Read transactions can be specified to use either a wrapped

or linear burst. During wrapped operation, accesses start at a selected location and continue for a configured number of locations in

a group wrap sequence. During linear operation accesses start at a selected location and continue in a sequential manner until the

read operation is terminated, when CS# returns High. Write transactions transfer one or more16-bit values.

Figure 1. Logic Block Diagram

Mandatory Signals

CS#

CK#

DQ[7:0]

RWDS

Optional Signals

CONTROL

LOGIC

ADDR

RESET#

RSTO#

INT#

PSC

PSC#

D E

E CC

C D

D EE

E RR

R S

Memory

Array

MIRRORBIT

Array

MEMORY ARRAY

Sense Amplifiers

SENSE AMPLIFIERS

Y DECODERS

Data Latch

ADDRESS

RWDS

GENERATOR

ADDR

The HyperFlash family consists of multiple densities, 1.8V/3.0V core and I/O, non-volatile, synchronous flash memory devices.

These devices have an 8-bit (1-byte) wide DDR data bus and use only word-wide (16-bit data) address boundaries. Read operations

provide 16 bits of data during each clock cycle (8 bits on each clock edge). Write operations take 16 bits of data from each clock

cycle (8 bits on each clock edge).

Each random read accesses a 32-byte length and aligned set of data called a page. Each page consists of a pair of 16-byte aligned

groups of array data called half-pages. Half-pages are aligned on 16-byte address boundaries. A read access requires two clock

cycles to define the target half-page address and the burst type, then an additional initial latency. During the initial latency period the

third clock cycle will specify the starting address within the target half-page. After the initial data value has been output, additional

data can be read from the Page on subsequent clock cycles in either a wrapped or linear manner. When configured in linear burst

mode, while a page is being burst out, the device will automatically fetch the next sequential page from the MirrorBit flash memory

array. This simultaneous burst output while fetching from the array allows for a linear sequential burst operation that can provide a

sustained output of 333 MB/s data rate (1-byte (8-bit data bus) * 2 (Data on both clock edges) * 166 MHz = 333 MB/s).

Document Number: 001-99198 Rev. *J

Page 4 of 96

S26KL512S/S26KS512S

S26KL256S/S26KS256S

S26KL128S/S26KS128S

Table 1. S26KS Address Map

Type

Word Address within a half-page (16 byte)

Word Address within Write Buffer Line (512 byte)

Half-pages (16 bytes) within Erase Sector (256 kB)

Write Buffer Lines (512 bytes) within Erase Sector (256 kB)

Total Number of Erase Sectors (256 kB)

Count

8 (word addresses)

256 (word addresses)

8192 (half-pages)

512 (lines)

256 (512 Mb)

128 (256 Mb)

64 (128 Mb)

Addresses

A2 – A0

A7 – A0

A16 – A3

A16 – A8

Amax – A17

Notes

16 bytes

512 bytes

The device control logic is subdivided into two parallel operating sections: the Host Interface Controller (HIC) and the Embedded

Algorithm Controller (EAC). The HIC monitors signal levels on the device inputs and drives outputs as needed to complete read and

write data transfers with the host system (HyperFlash master). The HIC delivers data from the currently entered address map on

read transfers; places write transfer address and data information into the EAC command memory; notifies the EAC of power

transition, and write transfers. The EAC looks in the command memory, after a write transfer, for legal command sequences and

performs the related Embedded Algorithms.

Changing the non-volatile data in the memory array requires a complex sequence of operations that are called Embedded

Algorithms (EA). The algorithms are managed entirely by the internal EAC. The main algorithms perform programming and erase of

the main flash array data. The host system writes command codes to the flash device address space. The EAC receives the

command, performs all the necessary steps to complete the command, and provides status information during the progress of an

EA.

The erased state of each memory bit is a logic 1. Programming changes a logic 1 (High) to a logic 0 (Low). Only an erase operation

is able to change a 0 to a 1. An erase operation must be performed on an entire 256-kbyte (or 4-kbyte for parameter sectors) aligned

group of data called a Sector. When shipped from Cypress all Sectors are erased.

Programming is done via a 512-byte Write Buffer. It is possible to write from one to 256 words, anywhere within the Write Buffer

before starting a programming operation. Within the flash memory array, each 512-byte aligned group of data is called a Line. A

programming operation transfers data from the volatile Write Buffer to a non-volatile memory array Line. The operation is called

Write Buffer Programming.

The Write Buffer is filled with 1s after reset or the completion of any operation using the Write Buffer. Any locations not written to a 0

by a Write to Buffer command are by default still filled with 1s. Any 1s in the Write Buffer do not affect data in the memory array

during a programming operation.

In addition to the mandatory signals (CS#, CK, CK#, DQ [7:0], RWDS) dedicated to the HyperBus, the device also includes optional

signals (RESET#, INT#, RSTO#, and Phase Shifted clocks PSC/PSC#).

When RESET# transitions from Low to High the device returns to the default state that occurs after an internal Power-On Reset

(POR).

The INT# output can provide an interrupt to the HyperFlash master to indicate when the HyperFlash transitions from busy to ready at

the end of a program or erase operation.

The RSTO# is an open-drain output used to indicate when a POR is occurring within the device and can be used as a system level

reset signal. Upon completion of the internal POR the RSTO# signal will transition from Low to high impedance after a user defined

timeout period has expired. Upon transition to the high impedance state the external pull-up resistance will pull RSTO# High and the

device immediately is placed into the Standby state.

PSC/PSC# are differential Phase Shifted Clock inputs used as a reference for RWDS edges instead of CK/CK#. Refer to

Section 1.1

DDR Center Aligned Read Strobe Functionality (DCARS) on page 6

for more details.

Document Number: 001-99198 Rev. *J

Page 5 of 96

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