ISDN Exchange Power Controller
(IEPC)
PEB 2025
CMOS IC
Features
q
Supplies power to up to four transmission lines
q
CCITT recommendations compatible for power feed at the
q
q
q
q
q
q
q
q
q
“S” interface
Each line is individually powered and controlled
Wide field of applications:
– two- and four wire transmission lines
– point-to-point configurations
– point-to-multipoint configurations
Maximum output current programmable up to 150 mA
Programmable switch-off characteristic by overcurrent
detection
Automatic restart after removing overload conditions
Status detectors for each line driver
Microprocessor compatible interface
Interrupt output for detection of any malfunction
High voltage CMOS technology (60 V)
P-LCC-28-R
P-DIP-22
Type
PEB 2025-N
PEB 2025-P
Version
V 1.5
V 1.5
Ordering Code
Q67100-H6300
Q67100-H6241
Package
P-LCC-28-R (SMD)
P-DIP-22
The IEPC is an integrated power controller especially designed for feeding two- and four wire
transmission lines. The IEPC is fully compatible to the CCITT recommendations on power feed at
the “S”-interface. So the IEPC can be used in PABX/Central Office and in intelligent NT´s.
The IEPC supplies power up to four transmission lines. Each line is individually powered and
controlled via microprocessor interface. An interrupt output signals any malfunction to the
microprocessor.
The high voltage CMOS technology (60 V) ensures a wide field of applications:
– two- and four wire transmission lines
– point-to-point configurations
– point-to-multipoint configurations etc.
1
05.92
PEB 2025
Programmable output current and thermal shut down guards the IEPC against overloads.
The IEPC offers a special transient permitted overload state. Momentary overloads within a
specified range e.g. by connecting a TE to a powered line, however, will not activate the current-
limit-circuits of the power controller. If overload is detected, the line driver will turn off according to
a time and current dependent turn off characteristic.
The IEPC offers an automatic restart-mode. In this case the IEPC tries to power up the line
periodically, thus the feeding of a line will return automatically after the overload-conditions are
removed.
Pin Configurations
(top view)
P-LCC-28-R
P-DIP-22
Semiconductor Group
2
PEB 2025
Pin Definitions and Functions
Pin No.
P-DIP-22
17
Pin No.
P-LCC-28
21, 22, 23
Symbol
Input (I)
Output (O)
I
Function
Supply Voltage:
This pin has to be
connected to the negative supply
voltage.
V
BAT
supplies power to all line
drivers.
Digital Supply Voltage:
+ 5V
Ground:
Digital
Note:
GND has to be connected to
ground battery (positive supply
voltage)
a-Line Feeding:
aF
i
are the line driver
outputs
Current Limit:
Using an external resistor
connected between
R
Imax
and GND, the
maximum limit is the same to all line
drivers.
Current Limit Characteristic:
By
connecting external capacitors between
CLC
i
and GND, the time-dependent turn
off-characteristics of the line drivers are
defined.
Chip Select:
A logic low on CS enables
RD and WR communication between the
processor and the IEPC.
Write:
A logic low on this pin, while CS is
low, enables the IEPC to accept
command words from the processor.
Read:
A low on this pin (while CS is low)
enables the IEPC to release status onto
the data bus for the processor.
Data Bus:
Control, status and command
information are transferred via this bus
between IEPC and processor.
Address Bus:
These inputs select the
internal registers while chip select is
active.
Reset:
A logic high on the RES input sets
the device into the initial state.
V
BAT
22
11
1
14
V
CC
GND
I
I
19, 18, 16,
15
12
25, 24, 20,
19
15
aF0 - aF3
O
I
R
Imax
21, 20, 14,
13
28, 26, 18,
16
CLC0 -
CLC3
I
1
2
CS
I
3
4
WR
I
2
3
RD
I
6, 5, 4
8, 7, 5
D0 - D2
I/O
8, 7
11, 9
A0, A1
I
10
13
RES
I
Semiconductor Group
3
PEB 2025
Pin Definitions and Functions
(cont’d)
Pin No.
P-DIP-22
9
Pin No.
P-LCC-28
12
Symbol
INT
Input (I)
Output (O)
O
Function
Interrupt:
Open drain output. If any
malfunction is detected by the IEPC, this
interrupt-pin is activ low.
Not connected
–
6, 10, 17, 27 N.C.
Figure 1
Functional Block Diagram
Semiconductor Group
4
PEB 2025
Figure 2
IEPC Architecture
Semiconductor Group
5
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