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5962-8767103KA

Description
OT PLD, 25ns, TTL, CDFP24,
CategoryProgrammable logic devices    Programmable logic   
File Size316KB,23 Pages
ManufacturerMonolithic Memories
Download Datasheet Parametric View All

5962-8767103KA Overview

OT PLD, 25ns, TTL, CDFP24,

5962-8767103KA Parametric

Parameter NameAttribute value
MakerMonolithic Memories
Reach Compliance Codeunknown
Other featuresPOWER-UP RESET
maximum clock frequency28.5 MHz
JESD-30 codeR-GDFP-F24
JESD-609 codee0
length15.367 mm
Dedicated input times12
Number of I/O lines2
Number of terminals24
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize12 DEDICATED INPUTS, 2 I/O
Output functionMIXED
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
Programmable logic typeOT PLD
propagation delay25 ns
Certification statusNot Qualified
Maximum seat height2.286 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyTTL
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
width10.29 mm
Base Number Matches1
REVISIONS
LTR
A
DESCRIPTION
Add vendor CAGE numbers 01295, 18324, and 34335 to the drawing. Added
device types 05 and 06 for vendor CAGE number 34335. Change to absolute
maximum ratings and table I. Editorial changes throughout.
Add device types 11 through 18 for vendor CAGE 34335. Removed vendor
CAGE 18324 as a source of supply for device types 05 and 06. Add vendor
CAGE 01295 to device types 15 through 18, packages L, K, and 3. Editorial
changes throughout.
Changes to table I; conditions for IIH, limits on ICC, and limits on some timing
conditions. Change pin 16 on case outline 3 to
OE . Add device type 19.
Editorial changes throughout.
DATE (YR-MO-DA)
90-03-29
APPROVED
M. Frye
B
91-05-09
M. Frye
C
93-02-19
M. Frye
D
E
Changes in accordance with NOR 5962-R142-93
Update drawing to current requirements. Editorial changes throughout. - gap
93-04-21
02-01-07
M. Frye
Raymond Monnin
THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED.
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
E
15
E
16
E
17
E
18
REV
SHEET
PREPARED BY
Kenneth Rice
E
19
E
20
E
1
E
2
E
3
E
4
E
5
E
6
E
7
E
8
E
9
E
10
E
11
E
12
E
13
E
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
CHECKED BY
Kenneth Rice
APPROVED BY
Michael A. Frye
DRAWING APPROVAL DATE
87-09-20
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
MICROCIRCUIT, DIGITAL,
MEMORY, BIPOLAR,
PROGRAMMING LOGIC,
MONOLITHIC SILICON
AMSC N/A
REVISION LEVEL
E
SIZE
A
SHEET
CAGE CODE
67268
1 OF
20
5962-87671
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E154-02
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