PCK9447BD datasheet, PDF - EEWORLD Datasheet

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PCK9447BD: Description3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer; Categorylogic logic; File Size76KB，17 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/; Environmental Compliance

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PCK9447BD Overview

3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer

PCK9447BD Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Philips Semiconductors (NXP Semiconductors N.V.)
package instruction	QFP, QFP32,.35SQ,32
Reach Compliance Code	unknow
JESD-30 code	S-PQFP-G32
MaximumI(ol)	0.024 A
Number of terminals	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP32,.35SQ,32
Package shape	SQUARE
Package form	FLATPACK
power supply	2.5/3.3 V
Prop。Delay @ Nom-Su	4.4 ns
Certification status	Not Qualified
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD

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PCK9447

3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer

Rev. 01 — 13 October 2005

Product data sheet

1. General description

The PCK9447 is a 3.3 V or 2.5 V compatible, 1 : 9 clock fan-out buffer targeted for high

performance clock tree applications. With output frequencies up to 350 MHz, and output

skews less than 150 ps, the device meets the needs of most demanding clock

applications.

The PCK9447 is speciﬁcally designed to distribute LVCMOS compatible clock signals up

to a frequency of 350 MHz. Each output provides a precise copy of the input signal with

near zero skew. The output buffers support driving of 50

Ω

terminated transmission lines

on the incident edge: each is capable of driving either one parallel terminated or two

series terminated transmission lines.

Two selectable independent LVCMOS compatible clock inputs are available, providing

support of redundant clock source systems. The PCK9447 CLK_STOP control is

synchronous to the falling edge of the input clock. It allows the start and stop of the output

clock signal only in a logic LOW state, thus eliminating potential output runt pulses.

Applying the OE control will force the outputs into high-impedance mode.

All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs

from ﬂoating. The device supports a 2.5 V or 3.3 V power supply and an ambient

temperature range of

−40 °C

to +85

°C.

The PCK9447 is pin and function compatible but

performance-enhanced to the PCK947.

2. Features

9 LVCMOS compatible clock outputs

2 selectable, LVCMOS compatible inputs

Maximum clock frequency of 350 MHz

Maximum clock skew of 150 ps

Synchronous output stop in logic LOW state eliminates output runt pulses

High-impedance output control

3.3 V or 2.5 V power supply

Drives up to 18 series terminated clock lines

amb

−40 °C

to +85

°C

Available in LQFP32 package

Supports clock distribution in networking, telecommunications and computer

applications

Pin and function compatible to PCK947

PCK9447BD Related Products

	PCK9447BD	PCK9447
Description	3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer	3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer

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