V
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2501
Phase-Locked Loop Clock Driver
Product Features
•
High-Performance, Phase-Locked-Loop Clock Distribution
•
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
•
Zero Input-to-Output delay
•
Low jitter: Cycle-to-Cycle jitter ±100ps max.
•
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
•
Operates at 3.3V V
CC
•
Wide range of Clock Frequencies up to 80 MHz
•
Package: Plastic 8-pin SOIC (W)
Product Description
The PI6C2501 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the CLK_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to CLK_OUT output will be nearly zero.
Application
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers, such as the
PI6C2509Q, or PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends using a zero-delay buffer and
an eighteen output non-zero-delay buffer. As shown in Figure 1,
this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Logic Block Diagram
Product Pin Configuration
AGND
GND
CLK_OUT
VCC
1
2
3
4
8
CLK_IN
AVCC
GND
FB_IN
CLK_IN
PLL
FB_IN
AV
CC
CLK_OUT
8-Pin
W
7
6
5
Feedback
C
Reference
Clock
Signal
Zero Delay
Buffer
PI6C2501
CLK_OUT
18 Outputs
Non-PLL
Buffer
17
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clock Signal and 17 Outputs
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PI6C2501
Phase-Locked Loop Clock Driver
Pin Functions
Pin Name
CLK _IN
FB
_
IN
CLK _O UT
AV
C C
AGND
V
C C
GND
Pin No.
8
5
3
7
1
4
2, 6
Type
I
I
O
Power
Ground
Power
Ground
D e s cription
Reference Clock input. CLK _IN allows spread spectrum clock input.
Feedback input. FB
_
IN provides the feedback signal to the internal PLL.
Clock output. This output provides a low- skew copy of CLK _IN. The output has an embedded
series- damping resistor.
Analog power supply. AV
C C
can be also used to bypass the PLL for test purpose. When AV
C C
is strapped to ground, PLL is bypassed and CLK _IN is buffered directly to the device outputs.
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply.
Ground.
DC Specifications
(Absolute maximum ratings over operating free-air temperature range)
Symbol
V
I
V
O
I
O_DC
Power
T
STG
Parame te r
Input voltage range
Output voltage range
DC output current
Maximum power dissipation at T
A
= 55
o
C in still air
Storage temperature
65
M in.
- 0.5
M ax.
V
CC
+0.5
100
1.0
150
Units
V
mA
W
o
C
Note:
Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device.
Parame te r
I
CC
C
I
C
O
Te s t Conditions
V
I
= V
CC
or GND; I
O
= 0
(1)
V
I
= V
CC
or GND
V
O
=V
CC
or GND
V
CC
3.6V
3.3V
M in.
Typ.
4
6
M ax.
10
Units
µA
pF
Note:
1. Continuous Output Current
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
V
I
T
A
Supply voltage
High level input voltage
Low level input voltage
Input voltage
Operating free- air temperature
0
0
Parame te r
M in.
3.0
2.0
0.8
V
CC
70
ºC
M ax.
3.6
V
Units
2
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PI6C2501
Phase-Locked Loop Clock Driver
Electrical Characteristics
(Over Recommended Operating Free-Air Temperature Range
Pull Up/Down Currents of PI6C2501, V
CC
= 3.0V)
Symbol
I
OH
Parame te r
Pull- up current
Pull- up current
Pull- down current
Pull- down current
Condition
Vout = 2.4V
Vout = 2.0V
Vout = 0.8V
Vout = 0.55V
M in.
M ax.
- 18
- 30
Units
I
OL
25
17
mA
AC Specifications
Symbol
F
CLK
D
CYI
(Timing requirements over recommended ranges of supply voltage and operating free-air temperature)
Parame te r
Clock frequency PI6C2501
Input clock duty cycle
Stabilization Time after power up
M in.
25
40
M ax.
80
60
1
Units
MHz
%
ms
Switching Characteristics
Parame te r
tphase error without jitter
Jitter, cycle- to- cycle
Duty cycle
tr, rise- time, 0.4V to 2.0V
tf, fall- time, 2.0V to 0.4V
(Over recommended ranges of supply voltage and operating free-air temperature, CL = 30pF)
From (Input)
CLK_IN
↑
at 100 & 66 MHz
At 100 & 66 MHz
To (Output)
FB_IN
↑
V
CC
= 3.3V ±0.3V, 0-70°C
M in.
150
100
45
1.0
1.1
Typ.
M ax.
+150
+100
55
Units
ps
%
ns
CLK_OUT
Note:
These switching parameters are guaranteed by design.
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PI6C2501
Phase-Locked Loop Clock Driver
Package Mechanical Information:
Plastic 8-pin SOIC Package.
8
.149
.157
3.78
3.99
.0099
.0196
0.25
x 45˚
0.50
1
.189
.196
4.80
5.00
0-8˚
.0075
.0098
0.40 .016
1.27 .050
.016
.026
0.406
0.660
REF
.053
.068
1.35
1.75
SEATING PLANE
.2284
.2440
5.80
6.20
0.19
0.25
.050
BSC
1.27
.013 0.330
.020 0.508
.0040 0.10
.0098 0.25
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Ordering Information
Orde ring Code
PI6C2501W
Package Name
W8
Package Type
8- pin 150- mil SO IC
Ope rating Range
Commercial
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
4
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