ESMT
Flash
FEATURES
Single supply voltage 2.7~3.6V
Standard, Dual and Quad SPI
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual/Quad max frequency: 50MHz / 86MHz /
100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI;
200MHz / 344MHz / 400MHz equivalent Quad SPI)
Low power consumption
- Active current: 35 mA
- Standby current: 30
μ
A
- Deep Power Down current: 5
μ
A
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Byte programming time: 7
μ
s (typical)
- Page programming time: 1.5 ms (typical)
Erase
- Chip erase time 25 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
Page Programming
- 256 byte per programmable page
F25L32QA
3V Only 32 Mbit Serial Flash Memory
with Dual and Quad
Lockable 512 bytes OTP security sector
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect (
WP
)
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L32QA –50PAG
F25L32QA –86PAG
F25L32QA –100PAG
F25L32QA –50PHG
F25L32QA –86PHG
F25L32QA –100PHG
Speed
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
Package
8 lead SOIC
8 lead SOIC
8 lead SOIC
16 lead SOIC
16 lead SOIC
16 lead SOIC
200mil
200mil
200mil
300mil
300mil
300mil
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The F25L32QA is a 32Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT’s
memory devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 16,384 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
is divided into 1024 uniform sectors with 4K byte each; 64
uniform blocks with 64K byte each. Sectors can be erased
individually without affecting the data in other sectors. Blocks can
be erased individually without affecting the data in other blocks.
Whole chip erase capabilities provide the flexibility to revise the
data in the device. The device has Sector, Block or Chip Erase
but no page erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2010
Revision: 1.1
1/40
ESMT
PIN DESCRIPTION
Symbol
SCK
Pin Name
Serial Clock
Serial Data Input /
Serial Data Input Output 0
Functions
To provide the timing for serial input and output operations
F25L32QA
SI / SIO
0
SO / SIO
1
Serial Data Output /
Serial Data Input Output 1
Chip Enable
Write Protect /
Serial Data Input Output 2
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO
pin to transfer commands, addresses or data serially into the device on the
rising edge of SCK and read data or status from the device on the falling edge
of SCK(for Dual/Quad mode).
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual/Quad
mode).
To activate the device when CE is low.
The Write Protect (
WP
) pin is used to enable/disable BPL bit in the status
register. / Bidirectional IO pin to transfer commands, addresses or data serially
into the device on the rising edge of SCK and read data or status from the
device on the falling edge of SCK (for Quad mode).
To temporality stop serial communication with SPI flash memory without
resetting the device. / Bidirectional IO pin to transfer commands, addresses or
data serially into the device on the rising edge of SCK and read data or status
from the device on the falling edge of SCK (for Quad mode).
To provide power.
CE
WP
/ SIO
2
HOLD / SIO
3
V
DD
V
SS
Hold /
Serial Data Input Output 3
Power Supply
Ground
FUNCTIONAL BLOCK DIAGRAM
Page Address
Latch / Counter
High Voltage
Generator
Memory
Array
Page Buffer
Status
Register
Byte Address
Latch / Counter
Y-Decoder
Command and Conrol Logic
Serial Interface
CE
SCK
SI
(SIO
0
)
SO
WP
HOLD
(SIO
1
) (SIO
2
) (SIO
3
)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2010
Revision: 1.1
3/40
Embedded System
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