DSP56001RC20 datasheet, PDF - EEWORLD Datasheet

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DSP56001RC20: Description24-Bit General Purpose Digital Signal Processor; CategoryThe embedded processor and controller Microcontrollers and processors; File Size506KB，64 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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DSP56001RC20 Overview

24-Bit General Purpose Digital Signal Processor

DSP56001RC20 Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
Parts packaging code	PGA
package instruction	PGA,
Contacts	88
Reach Compliance Code	unknow
Address bus width	16
barrel shifter	NO
bit size	24
boundary scan	NO
maximum clock frequency	20 MHz
External data bus width	24
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-CPGA-P88
JESD-609 code	e0
length	34.545 mm
low power mode	YES
Number of terminals	88
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.05 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	HCMOS
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	34.545 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER

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MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

24-Bit General Purpose

Digital Signal Processor

Order this document

by DSP56001/D

DSP56001

Pin Grid Array (PGA)

Available in an 88 pin ceramic

through-hole package.

Ceramic Quad Flat Pack (CQFP)

The DSP56001 is a member of Motorola’s family of

Available in a 132 pin, small footprint,

HCMOS, low-power, general purpose Digital Signal

surface mount package.

Processors. The DSP56001 features 512 words of full

speed, on-chip program RAM (PRAM) memory, two

Plastic Quad Flat Pack (PQFP)

256 word data RAMs, two preprogrammed data

Available in a 132 pin, small footprint,

ROMs, and special on-chip bootstrap hardware to per-

surface mount package.

mit convenient loading of user programs into the pro-

gram RAM. It is an off-the-shelf part since the program

memory is user programmable. The core of the processor consists of three execution units operating in parallel — the data ALU,

the address generation unit, and the program controller. The DSP56001 has MCU-style on-chip peripherals, program and data

memory, as well as a memory expansion port. The MPU-style programming model and instruction set make writing efficient, com-

pact code, straightforward.

The high throughput of the DSP56001 makes it well-suited for communication, high-speed control, numeric processing, computer

and audio applications. The key features which facilitate this throughput are:

•

Speed

•

Precision

•

Parallelism

At 16.5 million instructions per second (MIPS) with a 33 MHz clock, the DSP56001 can execute

a 1024 point complex Fast Fourier Transform in1.98 milliseconds (66,240 clock cycles).

The data paths are 24 bits wide thereby providing 144 dB of dynamic range; intermediate results

held in the 56-bit accumulators can range over 336 dB.

The data ALU, address arithmetic units, and program controller operate in parallel so that an in-

struction prefetch, a 24x24-bit multiplication, a 56-bit addition, two data moves, and two address

pointer updates using one of three types of arithmetic (linear, modulo, or reverse carry) can be

executed in a single instruction cycle. This parallelism allows a four coefficient Infinite Impulse Re-

sponse (IIR) filter section to be executed in only four cycles, the theoretical minimum for a single

multiplier architecture.

In addition to the three independent execution units, the DSP56001 has six on-chip memories,

three on-chip MCU style peripherals (Serial Communication Interface, Synchronous Serial Inter-

face, and Host Interface), a clock generator and seven buses (three address and four data), mak-

ing the overall system functionally complete and powerful, but also very low cost, low power, and

compact.

The three-stage instruction pipeline is essentially invisible to the programmer thus allowing

straightforward program development in either assembly language or a high-level language such

as ANSI C.

The 62 instruction mnemonics are MCU-like making the transition from programming micropro-

cessors to programming the DSP56001 digital signal processor as easy as possible. The orthog-

onal syntax supports control of the parallel execution units. This syntax provides 12,808,830 dif-

ferent instruction variations using the 62 instruction mnemonics. The no-overhead DO instruction

and the REPEAT (REP) instruction make writing straight-line code obsolete.

The DSP56001 is identical to the DSP56000 except that it has 512x24-bits of on-chip program

RAM instead of 3.75K of program ROM; a 32x24-bit bootstrap ROM for loading the program RAM

from either a byte-wide memory mapped ROM or via the Host Interface; and the on-chip X and Y

Data ROMs have been preprogrammed as positive Mu- and A-Law to linear expansion tables and

a full, four quadrant sine wave table, respectively.

As a CMOS part, the DSP56001 is inherently very low power; however, three other features can

reduce power consumption to an exceptionally low level.

— The WAIT instruction shuts off the clock in the central processor portion of the DSP56001.

— The STOP instruction halts the internal oscillator.

— Power increases linearly (approximately) with frequency; thus, reducing the clock frequency

reduces power consumption.

•

Integration

•

Invisible Pipeline

•

Instruction Set

•

DSP56000/DSP56001

Compatibility

•

Low Power

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA INC., 1992

Rev. 3

May 4, 1998

DSP56001RC20 Related Products

	DSP56001RC20	DSP56001	DSP56001FE20	DSP56001FC20	DSP56001RC27	DSP56001RC33	DSP56001FE33	DSP56001FE27	DSP56001FC33	DSP56001FC27
Description	24-Bit General Purpose Digital Signal Processor	24-Bit General Purpose Digital Signal Processor	24-Bit General Purpose Digital Signal Processor	24-Bit General Purpose Digital Signal Processor	24-Bit General Purpose Digital Signal Processor	24-Bit General Purpose Digital Signal Processor	24-Bit General Purpose Digital Signal Processor	24-Bit General Purpose Digital Signal Processor	24-Bit General Purpose Digital Signal Processor	24-Bit General Purpose Digital Signal Processor
Maker	Motorola ( NXP )	-	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )
Parts packaging code	PGA	-	QFP	QFP	PGA	PGA	QFP	QFP	QFP	QFP
package instruction	PGA,	-	QFP,	LFQFP,	PGA,	PGA,	QFP,	QFP,	LFQFP,	LFQFP,
Contacts	88	-	132	132	88	88	132	132	132	132
Reach Compliance Code	unknow	-	unknow	unknow	unknow	unknow	unknow	unknow	unknow	unknow
Address bus width	16	-	16	16	16	16	16	16	16	16
barrel shifter	NO	-	NO	NO	NO	NO	NO	NO	NO	NO
boundary scan	NO	-	NO	NO	NO	NO	NO	NO	NO	NO
maximum clock frequency	20 MHz	-	20 MHz	20 MHz	27 MHz	33 MHz	33 MHz	27 MHz	33 MHz	27 MHz
External data bus width	24	-	24	24	24	24	24	24	24	24
Format	FIXED POINT	-	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	-	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-CPGA-P88	-	S-CQFP-G132	S-PQFP-G132	S-CPGA-P88	S-CPGA-P88	S-CQFP-G132	S-CQFP-G132	S-PQFP-G132	S-PQFP-G132
JESD-609 code	e0	-	e0	e0	e0	e0	e0	e0	e0	e0
length	34.545 mm	-	22.352 mm	20 mm	34.545 mm	34.545 mm	22.352 mm	22.352 mm	20 mm	20 mm
low power mode	YES	-	YES	YES	YES	YES	YES	YES	YES	YES
Number of terminals	88	-	132	132	88	88	132	132	132	132
Package body material	CERAMIC, METAL-SEALED COFIRED	-	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	PGA	-	QFP	LFQFP	PGA	PGA	QFP	QFP	LFQFP	LFQFP
Package shape	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	-	FLATPACK	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY	GRID ARRAY	FLATPACK	FLATPACK	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.05 mm	-	4.318 mm	1.6 mm	3.05 mm	3.05 mm	4.318 mm	4.318 mm	1.6 mm	1.6 mm
Maximum supply voltage	5.5 V	-	5.5 V	5.5 V	5.5 V	5.25 V	5.25 V	5.5 V	5.25 V	5.5 V
Minimum supply voltage	4.5 V	-	4.5 V	4.5 V	4.5 V	4.75 V	4.75 V	4.5 V	4.75 V	4.5 V
Nominal supply voltage	5 V	-	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	-	YES	YES	NO	NO	YES	YES	YES	YES
technology	HCMOS	-	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG	-	GULL WING	GULL WING	PIN/PEG	PIN/PEG	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	2.54 mm	-	0.635 mm	0.5 mm	2.54 mm	2.54 mm	0.635 mm	0.635 mm	0.5 mm	0.5 mm
Terminal location	PERPENDICULAR	-	QUAD	QUAD	PERPENDICULAR	PERPENDICULAR	QUAD	QUAD	QUAD	QUAD
width	34.545 mm	-	22.352 mm	20 mm	34.545 mm	34.545 mm	22.352 mm	22.352 mm	20 mm	20 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	-	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER
ECCN code	-	-	-	-	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2

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