MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
24-Bit General Purpose
Digital Signal Processor
Order this document
by DSP56001/D
DSP56001
Pin Grid Array (PGA)
Available in an 88 pin ceramic
through-hole package.
Ceramic Quad Flat Pack (CQFP)
The DSP56001 is a member of Motorola’s family of
Available in a 132 pin, small footprint,
HCMOS, low-power, general purpose Digital Signal
surface mount package.
Processors. The DSP56001 features 512 words of full
speed, on-chip program RAM (PRAM) memory, two
Plastic Quad Flat Pack (PQFP)
256 word data RAMs, two preprogrammed data
Available in a 132 pin, small footprint,
ROMs, and special on-chip bootstrap hardware to per-
surface mount package.
mit convenient loading of user programs into the pro-
gram RAM. It is an off-the-shelf part since the program
memory is user programmable. The core of the processor consists of three execution units operating in parallel — the data ALU,
the address generation unit, and the program controller. The DSP56001 has MCU-style on-chip peripherals, program and data
memory, as well as a memory expansion port. The MPU-style programming model and instruction set make writing efficient, com-
pact code, straightforward.
The high throughput of the DSP56001 makes it well-suited for communication, high-speed control, numeric processing, computer
and audio applications. The key features which facilitate this throughput are:
•
Speed
•
Precision
•
Parallelism
At 16.5 million instructions per second (MIPS) with a 33 MHz clock, the DSP56001 can execute
a 1024 point complex Fast Fourier Transform in1.98 milliseconds (66,240 clock cycles).
The data paths are 24 bits wide thereby providing 144 dB of dynamic range; intermediate results
held in the 56-bit accumulators can range over 336 dB.
The data ALU, address arithmetic units, and program controller operate in parallel so that an in-
struction prefetch, a 24x24-bit multiplication, a 56-bit addition, two data moves, and two address
pointer updates using one of three types of arithmetic (linear, modulo, or reverse carry) can be
executed in a single instruction cycle. This parallelism allows a four coefficient Infinite Impulse Re-
sponse (IIR) filter section to be executed in only four cycles, the theoretical minimum for a single
multiplier architecture.
In addition to the three independent execution units, the DSP56001 has six on-chip memories,
three on-chip MCU style peripherals (Serial Communication Interface, Synchronous Serial Inter-
face, and Host Interface), a clock generator and seven buses (three address and four data), mak-
ing the overall system functionally complete and powerful, but also very low cost, low power, and
compact.
The three-stage instruction pipeline is essentially invisible to the programmer thus allowing
straightforward program development in either assembly language or a high-level language such
as ANSI C.
The 62 instruction mnemonics are MCU-like making the transition from programming micropro-
cessors to programming the DSP56001 digital signal processor as easy as possible. The orthog-
onal syntax supports control of the parallel execution units. This syntax provides 12,808,830 dif-
ferent instruction variations using the 62 instruction mnemonics. The no-overhead DO instruction
and the REPEAT (REP) instruction make writing straight-line code obsolete.
The DSP56001 is identical to the DSP56000 except that it has 512x24-bits of on-chip program
RAM instead of 3.75K of program ROM; a 32x24-bit bootstrap ROM for loading the program RAM
from either a byte-wide memory mapped ROM or via the Host Interface; and the on-chip X and Y
Data ROMs have been preprogrammed as positive Mu- and A-Law to linear expansion tables and
a full, four quadrant sine wave table, respectively.
As a CMOS part, the DSP56001 is inherently very low power; however, three other features can
reduce power consumption to an exceptionally low level.
— The WAIT instruction shuts off the clock in the central processor portion of the DSP56001.
— The STOP instruction halts the internal oscillator.
— Power increases linearly (approximately) with frequency; thus, reducing the clock frequency
reduces power consumption.
•
Integration
•
Invisible Pipeline
•
Instruction Set
•
DSP56000/DSP56001
Compatibility
•
Low Power
This document contains information on a new product. Specifications and information herein are subject to change without notice.
©
MOTOROLA INC., 1992
Rev. 3
May 4, 1998
ADDRESS
GENERATION
UNIT
PORT B
OR HOST
15
BOOTSTRAP
ROM
32X24
PROGRAM
RAM
512X24
YAB
XAB
PAB
EXTERNAL ADDRESS
ADDRESS
BUS
SWITCH
Y MEMORY
RAM
256X24
SINE ROM
256X24
9
PORT C
AND/OR
SSI, SCI
ON-CHIP
PERIPHERALS:
HOST, SSI,
SCI, PI/O
BUS
CONTROL
7
INTERNAL DATA
BUS SWITCH
AND BIT
MANIPULATION
UNIT
YDB
XDB
PDB
GDB
EXTERNAL
DATA BUS
SWITCH
DATA
CLOCK
GENERATOR
PROGRAM
ADDRESS
GENERATOR
PROGRAM
DECODE
CONTROLLER
PROGRAM
INTERRUPT
CONTROLLER
DATA ALU
24X24+56
→
56-BIT MAC
TWO 56-BIT ACCUMULATORS
MODB/IRQB
EXTAL
XTAL
MODA/IRQA
RESET
16 BITS
24 BITS
Figure 1. DSP56001 Block Diagram
In the USA:
For technical assistance call:
DSP Applications Helpline (512) 891-3230
For availability and literature call your local Motorola Sales Office or Authorized Motorola Distributor.
For free application software and information call the Dr. BuB electronic bulletin board:
9600/4800/2400/1200/300 baud
(512) 891-3771
(8 data bits, no parity, 1 stop)
In Europe, Japan and Asia Pacific
Contact your regional sales office or Motorola distributor.
MOTOROLA
2
DSP56001
PORT A
X MEMORY
RAM
256X24
µ/A
ROM
256X24
SIGNAL DESCRIPTION
The DSP56001 is available in 132 pin surface mount (CQFP and
PQFP) or an 88-pin pin-grid array packaging. Its input and output sig-
nals are organized into seven functional groups which are listed below
and shown in Figure 1.
Port A Address and Data Buses
Port A Bus Control
Interrupt and Mode Control
Power and Clock
Host Interface or Port B I/O
Serial Communications Interface or Port C I/O
Synchronous Serial Interface or Port C I/O
Read Enable (RD)
This three-state output is asserted to read external memory on the
data bus D0-D23. This pin is three-stated during RESET.
Write Enable (WR)
This three-state output is asserted to write external memory on the
data bus D0-D23. This pin is three-stated during RESET.
Bus Request (BR/WT)
The bus request input BR allows another device such as a processor
or DMA controller to become the master of external data bus D0-D23
and external address bus A0-A15. When operating mode register
(OMR) bit 7 is clear and BR is asserted, the DSP56001 will always re-
lease the external data bus D0-D23, address bus A0-A15, and bus
control pins PS, DS, X/Y, RD, and WR (i. e., Port A), by placing these
pins in the high-impedance state after execution of the current instruc-
tion has been completed.
The BR pin should be pulled up when not
in use.
If OMR bit 7 is set, this pin is an input that allows an external device to
force wait states during an external Port A operation for as long as WT
is asserted.
Bus Grant (BG/BS)
If OMR bit 7 is clear, this output is asserted to acknowledge an external
bus request after Port A has been released. If OMR bit 7 is set, this pin
is bus strobe and is asserted when the DSP accesses Port A. This pin
is three-stated during RESET.
PORT A ADDRESS AND DATA BUS
Address Bus (A0-A15)
These three-state output pins specify the address for external program
and data memory accesses. To minimize power dissipation, A0-A15
do not change state when external memory spaces are not being ac-
cessed.
Data Bus (D0-D23)
These pins provide the bidirectional data bus for external program and
data memory accesses. D0-D23 are in the high-impedance state when
the bus grant signal is asserted.
PORT A BUS CONTROL
Program Memory Select (PS)
This three-state output is asserted only when external program mem-
ory is referenced. This pin is three-stated during RESET.
Data Memory Select (DS)
This three-state output is asserted only when external data memory is
referenced. This pin is three-stated during RESET.
X/Y Select (X/Y)
This three-state output selects which external data memory space (X
or Y) is referenced by data memory select (DS). This pin is three-stat-
ed during RESET.
HOST CONTROL
HREQ
H0-H7
INTERRUPT AND MODE CONTROL
Mode Select A/External Interrupt Request A (MODA/IRQA),
Mode Select B/External Interrupt Request B (MODB/IRQB)
These two inputs have dual functions: 1) to select the initial chip oper-
ating mode and 2) to receive an interrupt request from an external
source. MODA and MODB are read and internally latched in the DSP
when the processor exits the RESET state. Therefore these two pins
should be forced into the proper state during reset. After leaving the
RESET state, the MODA and MODB pins automatically change to ex-
ternal interrupt requests IRQA and IRQB. After leaving the reset state
the chip operating mode can be changed by software. IRQA and IRQB
may be programmed to be level sensitive or negative edge triggered.
When edge triggered, triggering occurs at a voltage level and is not di-
rectly related to the fall time of the interrupt signal, however, the prob-
ability of noise on IRQA or IRQB generating multiple interrupts increas-
es with increasing fall time of the interrupt signal. These pins are inputs
during RESET.
Reset (RESET)
RXD
HOST DATA
BUS
HACK
HR/W
HEN
HA0
HA1
HA2
ADDRESS
DATA
A0-A15
D0-D23
PS
DS
RD
PORT A
PORT C
PORT B
TXD
SCLK
SC0
SC1
SCK
SRD
STD
SCI
BUS
CONTROL
WR
X/Y
BR/WT
BG/BS
DSP56001
SSI
This Schmitt trigger input pin is used to reset the DSP56001. When
RESET is asserted, the DSP56001 is initialized and placed in the reset
state. When the RESET signal is deasserted, the initial chip operating
mode is latched from the MODA and MODB pins. When coming out of
reset, deassertion occurs at a voltage level and is not directly related
to the rise time of the reset signal; however, the probability of noise on
RESET generating multiple resets increases with increasing rise time
of the reset signal.
POWER AND CLOCK
Power (Vcc), Ground (GND)
There are five sets of power and ground pins used for the four groups
of logic on the chip, two pairs for internal logic, one power and two
ground for Port A address and control pins, one power and two ground
for Port A data pins, and one pair for peripherals. Refer to the pin as-
signments in the
LAYOUT PRACTICES
section.
MODB/
IRQB
Figure 2. Functional Signal Groups
DSP56001
MOTOROLA
3
RESET
MODA/
IRQA
XTAL
EXTAL
VSS
VDD
External Clock/Crystal Input (EXTAL)
EXTAL may be used to interface the crystal oscillator input to an exter-
nal crystal or an external clock.
Crystal Output (XTAL)
This output connects the internal crystal oscillator output to an external
crystal. If an external clock is used, XTAL should not be connected.
Transmit Data (TXD)
This output transmits serial data from the SCI Transmit Shift Register.
Data changes on the negative edge of the transmit clock. This output
is stable on the positive edge of the transmit clock. TXD may be pro-
grammed as a general purpose I/O pin called PC1 when the SCI is not
being used. This pin is configured as a GPIO input pins during hard-
ware reset.
SCI Serial Clock (SCLK)
This bidirectional pin provides an input or output clock from which the
transmit and/or receive baud rate is derived in the asynchronous mode
and from which data is transferred in the synchronous mode. SCLK
may be programmed as a general purpose I/O pin called PC2 when
the SCI is not being used. This pin is configured as a GPIO input pins
during hardware reset.
HOST INTERFACE
Host Data Bus (H0-H7)
This bidirectional data bus is used to transfer data between the host
processor and the DSP56001. This bus is an input unless enabled by
a host processor read. H0-H7 may be programmed as general pur-
pose parallel I/O pins called PB0-PB7 when the Host Interface is not
being used. These pins are configured as a GPIO input pins during
hardware reset.
Host Address (HA0-HA2)
These inputs provide the address selection for each Host Interface
register. HA0-HA2 may be programmed as general purpose parallel
I/O pins called PB8-PB10 when the Host Interface is not being used.
These pins are configured as a GPIO input pins during hardware reset.
Host Read/Write (HR/W)
This input selects the direction of data transfer for each host processor
access. HR/W may be programmed as a general purpose I/O pin
called PB11 when the Host Interface is not being used. This pin is con-
figured as a GPIO input pins during hardware reset.
Host Enable (HEN)
This input enables a data transfer on the host data bus. When HEN is
asserted and HR/W is high, H0-H7 become outputs, and DSP56001
data may be read by the host processor, When HEN is asserted and
HR/W is low, H0-H7 become inputs and host data is latched inside the
DSP when HEN is deasserted. Normally a chip select signal, derived
from host address decoding and an enable clock, is used to generate
HEN. HEN may be programmed as a general purpose I/O pin called
PB12 when the Host Interface is not being used. This pin is configured
as a GPIO input pins during hardware reset.
Host Request (HREQ)
This open-drain output signal is used by the DSP56001 Host Interface
to request service from the host processor, DMA controller, or simple
external controller. HREQ may be programmed as a general purpose
I/O pin (not open-drain) called PB13 when the Host interface is not be-
ing used. HREQ should be pulled high when not in use. This pin is con-
figured as a GPIO input pins during hardware reset.
Host Acknowledge (HACK)
This input has two functions: 1) to receive a Host Acknowledge hand-
shake signal for DMA transfers and, 2) to receive a Host Interrupt Ac-
knowledge compatible with MC68000 Family processors. HACK may
be programmed as a general purpose I/O pin called PB14 when the
Host Interface is not being used. This pin is configured as a GPIO input
pins during hardware reset.
HACK should be pulled high when not
in use.
SYNCHRONOUS SERIAL INTERFACE (SSI)
Serial Control Zero (SC0)
This bidirectional pin is used for control by the SSI. SC0 may be pro-
grammed as a general purpose I/O pin called PC3 when the SSI is not
being used. This pin is configured as a GPIO input pins during hard-
ware reset.
Serial Control One (SC1)
This bidirectional pin is used for control by the SSI. SC1 may be pro-
grammed as a general purpose I/O pin called PC4 when the SSI is not
being used. This pin is configured as a GPIO input pins during hard-
ware reset.
Serial Control Two (SC2)
This bidirectional pin is used for control by the SSI. SC2 may be pro-
grammed as a general purpose I/O pin called PC5 when the SSI is not
being used. This pin is configured as a GPIO input pins during hard-
ware reset.
SSI Serial Clock (SCK)
This bidirectional pin provides the serial bit rate clock for the SSI when
only one clock is used. SCK may be programmed as a general pur-
pose I/O pin called PC6 when the SSI is not being used. This pin is
configured as a GPIO input pins during hardware reset.
SSI Receive Data (SRD)
This input pin receives serial data into the SSI Receive Shift Register.
SRD may be programmed as a general purpose I/O pin called PC7
when the SSI is not being used. This pin is configured as a GPIO input
pins during hardware reset.
SSI Transmit Data (STD)
This output pin transmits serial data from the SSI Transmit Shift Reg-
ister. STD may be programmed as a general purpose I/O pin called
PC8 when the SSI is not being used. This pin is configured as a GPIO
input pins during hardware reset.
SERIAL COMMUNICATIONS INTERFACE (SCI)
Receive Data (RXD)
This input receives byte-oriented data into the SCI Receive Shift Reg-
ister. Input data is sampled on the positive edge of the Receive Clock.
RXD may be programmed as a general purpose I/O pin called PC0
when the SCI is not being used. This pin is configured as a GPIO input
pins during hardware reset.
MOTOROLA
4
DSP56001
DSP56001 Electrical Characteristics
Electrical Specifications
The DSP is fabricated in high density CMOS with TTL compatible inputs and outputs.
Maximum Ratings (V
SS
= 0 Vdc)
Rating
Supply Voltage
All Input Voltages
Current Drain per Pin
excluding Vcc and V
SS
Operating Temperature Range
Storage Temperature
Symbol
Vcc
Vin
I
T
J
Tstg
Value
-0.3 to +7.0
V
SS
- 0.5 to Vcc + 0.5
10
-40 to +105
-55 to +150
Unit
V
V
mA
°C
°C
Maximum Electrical Ratings
Thermal Characteristics - PGA Package
Characteristics
Thermal Resistance - Ceramic
Junction to Ambient
Junction to Case (estimated)
Symbol
Θ
JA
Θ
JC
Value
27
6.5
Rating
°C/W
°C/W
Thermal Characteristics - CQFP Package
Characteristics
Thermal Resistance - Ceramic
Junction to Ambient
Junction to Case (estimated)
Symbol
Θ
JA
Θ
JC
Value
40
7.0
Rating
°C/W
°C/W
Thermal Characteristics - PQFP Package
Characteristics
Thermal Resistance - Plastic
Junction to Ambient
Junction to Case (estimated)
Symbol
Θ
JA
Θ
JC
Value
38
13.0
Rating
°C/W
°C/W
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal
precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either Gnd or Vcc).
DSP56001
MOTOROLA
5
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