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8T49N205A-999NLGI

Description
Clock Synthesizer / Jitter Cleaner FemtoClock NG UFT Phase Build-Out
Categorysemiconductor    Analog mixed-signal IC   
File Size725KB,41 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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8T49N205A-999NLGI Overview

Clock Synthesizer / Jitter Cleaner FemtoClock NG UFT Phase Build-Out

8T49N205A-999NLGI Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology, Inc.)
Product CategoryClock Synthesizer / Jitter Cleaner
RoHSDetails
Package / CaseVFQFPN-40
PackagingTray
Height0.9 mm
Length6 mm
Width6 mm
Moisture SensitiveYes
Factory Pack Quantity490
FemtoClock
®
NG Universal Frequency
Translator with Phase Build-Out
IDT8T49N205I
DATA SHEET
General Description
The IDT8T49N205I is a highly flexible FemtoClock® NG general
purpose, low phase noise Frequency Translator / Synthesizer with
Phase Build-Out (PBO) suitable for networking and communications
applications. It is able to generate any output frequency in the
0.98MHz - 312.5MHz range and most output frequencies in the
312.5MHz - 1,300MHz range (see Table 3 for details). A wide range
of input reference clocks and a range of low-cost fundamental mode
crystal frequencies may be used as the source for the output
frequency.
The IDT8T49N205I has three operating modes to support a very
broad spectrum of applications:
1
Frequency Synthesizer
Features
Fourth Generation FemtoClock® NG technology
Universal Frequency Translator/Frequency Synthesizer
Zero ppm frequency translation
Both outputs may be set to use 2.5V or 3.3V output levels
Programmable output frequency: 0.98MHz up to 1,300MHz
Two outputs, individually programmable as LVPECL or LVDS
Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz - 710MHz
Phase Build-Out minimizes output phase change on switchover
Crystal input frequency range: 16MHz - 40MHz
Two factory-set register configurations for power-up default state
Synthesizes output frequencies from a 16MHz - 40MHz
fundamental mode crystal.
Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
Applications: Networking & Communications.
Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
2) High-Bandwidth Frequency Translator
Power-up default configuration pin or register selectable
Configurations customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
RMS phase jitter at 155.52MHz, using a 40MHz crystal
(12kHz - 20MHz): 378fs (typical), Low Bandwidth Mode (FracN)
Output supply voltage modes:
V
CC
/V
CCA
/V
CCO
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V
2.5V/2.5V/2.5V
-40°C to 85°C ambient operating temperature
3) Low-Bandwidth Frequency Translator
Pin Assignment
LOCK_IND
V
CCO
OE0
OE1
nQ0
nQ1
V
CC
V
EE
nc
nc
S_A0
S_A1
CONFIG
SCLK
SDATA
V
CC
PLL_BYPASS
nc
This device provides two factory-programmed default power-up
configurations burned into One-Time Programmable (OTP) memory.
The configuration to be used is selected by the CONFIG pin. The two
configurations are specified by the customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices. The two configurations may be completely independent of
one another.
One usage example might be to install the device on a line card with
two optional daughter cards: an OC-12 option requiring a 622.08MHz
LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet
option requiring a 125MHz LVPECL clock translated from the same
19.44MHz input reference.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured. However, these settings
would have to be re-written next time the device powers-up.
Q0
CLK_ACTIVE
nc
LF0
LF1
V
EE
V
CCA
HOLDOVER
CLK0BAD
CLK1BAD
XTALBAD
31
32
33
34
30 29 28 27 26 25 24 23 22 21
20
19
IDT8T49N205I
Q1
18
17
16
15
14
13
12
11
40 Lead VFQFN
35
6mm x 6mm x 0.925mm
36
EPad 4.65mm x 4.65mm
37
NL Package
38
39
40
1
XTAL_IN
2 3 4
V
CC
CLK_SEL
XTAL_OUT
5 6
CLK0
nCLK0
7
V
CC
8
V
EE
9 10
CLK1
Top View
IDT8T49N205ANLGI REVISION B JULY 9, 2013
1
©2013 Integrated Device Technology, Inc.
nCLK1

8T49N205A-999NLGI Related Products

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Description Clock Synthesizer / Jitter Cleaner FemtoClock NG UFT Phase Build-Out Clock Synthesizer / Jitter Cleaner FemtoClock NG UFT Phase Build-Out
Product Attribute Attribute Value Attribute Value
Manufacturer IDT (Integrated Device Technology, Inc.) IDT (Integrated Device Technology, Inc.)
Product Category Clock Synthesizer / Jitter Cleaner Clock Synthesizer / Jitter Cleaner
RoHS Details Details
Package / Case VFQFPN-40 VFQFPN-40
Packaging Tray Reel
Height 0.9 mm 0.9 mm
Length 6 mm 6 mm
Width 6 mm 6 mm
Moisture Sensitive Yes Yes
Factory Pack Quantity 490 5000
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