This parameter is periodically sampled and not 100% tested.
3
NM34C02 Rev. D.2
www.fairchildsemi.com
NM34C02 2K-Bit Standard 2-Wire Bus Interface
AC Conditions of Test
Input Pulse Levels
Input Rise and Fall Times
Input & Output Timing Levels
Output Load
V
CC
x 0.1 to V
CC
x 0.9
10 ns
V
CC
x 0.5
1 TTL Gate and C
L
= 100 pF
Read and Write Cycle Limits (Standard and Low V
CC
Range 2.7V - 4.5V)
Symbol
f
SCL
T
I
Parameter
SCL Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
IN
Pulse width)
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time - NM34C02
- NM34C02L, NM34C02LZ
100 KHz
Min
Max
100
100
0.3
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
300
10
15
3.5
400 KHz
Min
Max
400
50
0.1
1.3
0.6
1.5
0.6
0.6
0
100
0.3
300
0.6
50
10
15
0.9
Units
KHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
WR
(Note 3)
Note 3:
The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM34C02 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
4
NM34C02 Rev. D.2
www.fairchildsemi.com
NM34C02 2K-Bit Standard 2-Wire Bus Interface
Bus Timing
tF
tHIGH
tLOW
SCL
tLOW
tR
SDA
SDA
OUT
Background Information (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional com-
munication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condi-
tion.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROMs, etc., a device type identifier string must
follow the START condition. For EEPROMs, this 4-bit string is
1010. Also refer the
Addressing the WP Register
section.
As shown below, although the EEPROMs on the IIC bus may be
configured in any manner required, the total memory addressed can
not exceed 16K (16,384 bits) on the Standard IIC protocol. EE-
PROM memory address programming is controlled by 2 methods:
• Hardware configuring the A0, A1, and A2 pins (Device
Address pins) with pull-up or pull-down resistors.
All unused
pins must be grounded
(tied to V
SS
).
• Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]—[DEVICE ADDRESS]—[PAGE BLOCK
ADDRESS]—[BYTE ADDRESS]
,,
tSU:STA
tHD:STA
IN
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tDH
tAA
DS012821-4
DEFINITIONS
BYTE
PAGE
8 bits of data
16 sequential addresses (one byte
each) that may be programmed
during a 'Page Write' programming
cycle
2,048 (2K) bits organized into 16
pages of addressable memory. (8
bits) x (16 bytes) x (16 pages) = 2,048
bits
Any IIC device CONTROLLING the
transfer of data (such as a micropro-
cessor)
Device being controlled (EEPROMs
are always considered Slaves)
Device currently SENDING data on
the bus (may be either a Master or
Slave).
Device currently receiving data on the
bus (Master or Slave)
PAGE BLOCK
MASTER
SLAVE
TRANSMITTER
RECEIVER
Example of 16K of Memory on 2-Wire Bus
VCC
SDA
SCL
VCC
VCC
VCC
VCC
NM34C02L
A0 A1 A2 VSS
NM24C02
A0 A1 A2 VSS
NM24C04
A0 A1 A2 VSS
NM24C08
A0 A1 A2 VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
DS012821-5
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF.
Specific timing and addressing considerations are described in greater detail in the following sections.
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