TLS202A1
Adjustable Linear Voltage Post Regulator
TLS202A1MBV
Data Sheet
Rev. 1.0, 2015-06-22
Automotive Power
Adjustable Linear Voltage Post Regulator
TLS202A1MBV
1
Features
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Overview
Adjustable Output Voltage from 1.2 V to 5.25 V
Output Voltage Accuracy of ±3 %
Output Currents up to 150 mA
Extended Input Voltage Operating Range of 2.7 V to 18 V
Low Dropout Voltage: typ. 290mV
Very Low Current Consumption: typ. 50 µA
Very High PSRR: typ. 65dB at 10kHz
Output Current Limitation
Short Circuit protected
Overtemperature Shutdown
Wide Temperature Range From -40 °C up to 150 °C
Suitable for Use in Automotive Electronics as Post Regulator
Green Product (RoHS compliant)
AEC Qualified
PG-SCT595
Functional Description
The TLS202A1 is a monolithic integrated adjustable linear voltage post regulator for load currents up to 150 mA.
The IC regulates an input voltage
V
I
in the range of 2.7 V
≤
V
I
≤
18 V to an adjustable output voltage of 1.2 V to
5.25 V with a precision of ±3 %. The TLS202A1 is especially designed for applications requiring very low standby
currents, e.g. with a permanent connection to preregulators like DCDC converters. The regulator is not designed
to operate with a direct connection to the battery. The device is available in a very small surface mounted PG-
SCT595 package. The device is designed for the harsh environment of automotive applications. Therefore it is
protected against overload, short circuit and overtemperature conditions by the implemented output current
limitation and the overtemperature shutdown circuit. The TLS202A1 can be also used in all other applications
requiring a stabilized voltage of 1.2 V to 5.25 V.
Choosing External Components
The input capacitor
C
I
is recommended for compensating line influences. The output capacitor
C
Q
is necessary
for the stability of the regulating circuit. Stability is guaranteed at values specified in
“Functional Range” on
Page 6
within the whole operating temperature range.
Type
TLS202A1MBV
Data Sheet
Package
PG-SCT595
2
Marking
20
Rev. 1.0, 2015-06-22
TLS202A1
Block Diagram
2
Block Diagram
I
Q
Current Limitation
ADJ
Driver
Bandgap
Reference
GND
Temperature
Shutdown
Figure 1
Block Diagram
Data Sheet
3
Rev. 1.0, 2015-06-22
TLS202A1
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment PG-SCT595
5
4
1
2
3
SCT595.vsd
Figure 2
Pin Configuration Package PG-SCT595-5
3.2
Pin Definitions and Functions
Pin
1
Symbol
I
Function
Input.
IC supply.
For compensation line influences, a capacitor of 220nF close to the IC pins
recommended.
Ground Reference.
Internally connected to Pin 5. Connect to heatsink area.
For thermal reasons both ground Pins 2 and 5 have to be soldered.
Output.
Block to GND with a capacitor close to the IC terminals, respecting capacitance and ESR
requirements given in the
“Functional Range” on Page 6.
Adjust.
The reference voltage can be connected directly to the output Q or by a voltage divider for higher
output voltages (see
“Application Information” on Page 15).
Ground Reference.
Internally connected to Pin 2. Connect to heatsink area.
For thermal reasons both ground Pins 2 and 5 have to be soldered.
2
GND
3
Q
4
ADJ
5
GND
Data Sheet
4
Rev. 1.0, 2015-06-22
TLS202A1
General Product Characteristics
4
4.1
General Product Characteristics
Absolute Maximum Ratings
Table 1
Parameter
Input I
Voltage
Output Q
Voltage
Adjust ADJ
Voltage
Absolute Maximum Ratings
1)
T
j
= -40 °C to +150 °C; all voltages with respect to ground,
(unless otherwise specified)
Symbol
Min.
Values
Typ.
–
–
–
–
–
–
–
Max.
20
5.5
5.5
150
150
4
750
V
V
V
°C
°C
kV
V
Unit
Note /
Test Condition
–
–
–
–
–
Human Body Model
(HBM)
2)
Number
V
I
V
Q
V
ADJ
T
j
T
stg
-0.3
-0.3
-0.3
-40
-50
P_4.1.1
P_4.1.2
P_4.1.3
P_4.1.4
P_4.1.5
P_4.1.6
Temperature
Junction temperature
Storage temperature
ESD Susceptibility
ESD Absorption
ESD Absorption
V
ESD,HBM
-4
V
ESD,CDM
-750
Charge Device
P_4.1.7
3)
Model (CDM) at all
pins
1) not subject to production test, specified by design
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
5
Rev. 1.0, 2015-06-22
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