FemtoClock
®
Crystal-to-LVDS
Clock Generator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
844001I
DATA SHEET
G
ENERAL
D
ESCRIPTION
The 844001I is a Fibre Channel Clock Generator. The 844001I uses an
18pF parallel resonant crystal over the range of 20.4MHz - 28.3MHz.
For Fibre Channel applications, a 26.5625MHz crystal is used. The
frequency select pin allows the device to generate either 106.25MHz
or 212.5MHz from a 26.5625MHz crystal. To generate 187.5MHz for
12Gb Ethernet, a 23.4375MHz crystal is used. The 844001I uses IDT’s
3
rd
generation low phase noise VCO technology and can achieve
<1ps typical rms phase jitter, easily meeting Fibre Channel and
Ethernet jitter requirements. The 844001I is packaged in a small
8-pin TSSOP, making it ideal for use in systems with limited board
space.
F
EATURES
•
One Differential LVDS output
•
Crystal oscillator interface, 18pF parallel resonant crystal
(20.4MHz - 28.3MHz)
•
Output frequency range: 81.66MHz - 226.66MHz
•
VCO range: 490MHz - 680MHz
•
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.74ps (typical)
•
3.3V or 2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
•
For functional replacement part use 8T49N242
C
OMMON
C
ONFIGURATION
T
ABLE
- F
IBRE
C
HANNEL
, 12Gb E
THERNET
Inputs
Crystal Frequency (MHz)
26.5625
26.5625
23.4375
FREQ_SEL
1
0
0
M
24
24
24
N
6
3
3
Multiplication
Value M/N
4
8
8
Output Frequency
(MHz)
106.25
212.5
187.5
B
LOCK
D
IAGRAM
FREQ_SEL
Pullup
P
IN
A
SSIGNMENT
÷3
0
Q
nQ
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
nQ
FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
÷6
M = ÷24
(fixed)
1
844001I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
844001I REVISION A 6/2/2016
1
©2016 Integrated Device Technology, Inc.
844001I DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT,
XTAL_IN
FREQ_SEL
nQ, Q
V
DD
Power
Power
Input
Input
Output
Power
Pullup
Type
Description
Analog supply pin.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Frequency select pin.
Differential clock outputs. LVDS interface levels.
Core supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
FEMTOCLOCK® CRYSTAL-TO-LVDS
CLOCK GENERATOR
2
REVISION A 6/2/2016
844001I DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
101.7°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.12
Typical
3.3
3.3
Maximum
3.465
V
DD
115
12
Units
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.12
Typical
2.5
2.5
Maximum
2.625
V
DD
110
12
Units
V
V
mA
mA
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
FREQ_SEL
FREQ_SEL
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
T
ABLE
3D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Parameter
Differential Output Voltage
OD
Test Conditions
Minimum
350
1.225
Typical
415
1.325
Maximum
480
50
1.425
50
Units
mV
mV
V
mV
Δ
V
V
OS
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Δ
V
OS
NOTE: Please refer to Parameter Measurement Information for output information.
REVISION A 6/2/2016
3
FEMTOCLOCK® CRYSTAL-TO-LVDS
CLOCK GENERATOR
844001I DATA SHEET
T
ABLE
3E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Parameter
Differential Output Voltage
OD
Test Conditions
Minimum
300
1.0
Typical
390
1.2
Maximum
480
50
1.325
50
Units
mV
mV
V
mV
Δ
V
V
OS
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Δ
V
OS
NOTE: Please refer to Parameter Measurement Information for output information.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: It is not recommended to overdrive the crystal input with an external clock.
20.4
Test Conditions
Minimum
Typical
Fundamental
28.3
50
7
1
MHz
Ω
pF
mW
Maximum
Units
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
106.25MHz @ Integration Range:
637kHz - 10MHz
187.5MHz @ Integration Range:
637kHz - 10MHz
212.5MHz @ Integration Range:
637kHz - 10MHz
20% to 80%
FREQ_SEL = 1
FREQ_SEL = 0
175
48
45
Test Conditions
Minimum
81.66
0.74
0.48
0.70
500
52
55
Typical
Maximum
226.66
Units
MHz
ps
ps
ps
ps
%
%
tjit(Ø)
RMS Phase Jitter ( Random);
NOTE 1
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
106.25MHz @ Integration Range:
637kHz - 10MHz
187.5MHz @ Integration Range:
637kHz - 10MHz
212.5MHz @ Integration Range:
637kHz - 10MHz
20% to 80%
FREQ_SEL = 1
FREQ_SEL = 0
175
48
45
Test Conditions
Minimum
81.66
0.97
0.58
0.95
500
52
55
Typical
Maximum
226.66
Units
MHz
ps
ps
ps
ps
%
%
tjit(Ø)
RMS Phase Jitter ( Random);
NOTE 1
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
FEMTOCLOCK® CRYSTAL-TO-LVDS
CLOCK GENERATOR
4
REVISION A 6/2/2016
844001I DATA SHEET
T
YPICAL
P
HASE
N
OISE AT
106.25MH
Z
@3.3V
0
-10
-20
-30
-40
-50
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.74ps (typical)
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
Raw Phase Noise Data
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
212.5MH
Z
@3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
Fibre Channel Filter
212.5MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.70ps (typical)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
REVISION A 6/2/2016
5
FEMTOCLOCK® CRYSTAL-TO-LVDS
CLOCK GENERATOR
Embedded System
京公网安备 11010802033920号
EEWORLD
