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74VHC03MTR

Description
Logic Gates Quad 2-Input NOR
Categorylogic    logic   
File Size161KB,11 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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74VHC03MTR Overview

Logic Gates Quad 2-Input NOR

74VHC03MTR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeSOIC
package instructionSOP-14
Contacts14
Reach Compliance Codeunknown
seriesAHC/VHC
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length8.65 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.008 A
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristicsOPEN-DRAIN
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply2/5.5 V
Prop。Delay @ Nom-Sup8.5 ns
propagation delay (tpd)13 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9 mm
Base Number Matches1
74VHC03
QUAD 2-INPUT OPEN DRAIN NAND GATE
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 3.7ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 03
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (MAX.)
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74VHC03 is an advanced high-speed CMOS
QUAD 2-INPUT OPEN DRAIN NAND GATE
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
This device can, with an external pull-up resistor,
be used in wired AND configuration. This device
can also be used as a led driver and in any other
application requiring a current sink.
Figure 1: Pin Connection And IEC Logic Symbols
O
et
l
so
b
ro
P
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uc
d
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t(
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
O
-
so
b
te
le
ro
P
uc
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T&R
74VHC03MTR
74VHC03TTR
November 2004
Rev. 4
1/11

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