V62C21164096
256K x 16, 0.20
µm
CMOS STATIC RAM
PRELIMINARY
s
s
s
s
s
s
s
s
CILETIV LESOM
Features
A
0
A
6
A
7
A
8
A
9
I/O
1
I/O
16
UBE
LBE
OE
WE
CE
1
CE
2
Description
The V62C21164096 is a 4,194,304-bit static
random-access memory organized as 262,144
words by 16 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing with
common system bus structures.
High-speed: 70, 85 ns
Ultra low CMOS standby current of 4µA (max.)
Fully static operation
All inputs and outputs directly TTL compatible
Three state outputs
Ultra low data retention current (V
CC
= 1.2V)
Operating voltage: 2.3V – 3.0V
Packages
– 44-pin TSOP (Standard)
– 48-Ball CSP BGA (8mm x 10mm)
Functional Block Diagram
V
CC
Row
Decoder
1024 x 4096
Memory Array
GND
Column I/O
Input
Data
Circuit
Column Decoder
A
10
A
17
Control
Circuit
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
–40°C to +85°C
Package Outline
T
•
•
B
•
•
Access Time (ns)
70
•
•
85
•
•
L
•
Power
LL
•
•
Temperature
Mark
Blank
I
V62C21164096 Rev. 1.6 October 2001
1
V62C21164096
UBE, LBE Byte Enable
Active low inputs. These inputs are used to enable
the upper or lower data byte.
Write Enable Input
WE
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
I/O
1
–I/O
16
Data Input and Data Output Ports
These 16 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
GND
Power Supply
Ground
A
0
–A
17
Address Inputs
These 18 address inputs select one of the 256K x
16 bit segments in the RAM.
CE
1
, CE
2
* Chip Enable Inputs
CE
1
is active LOW and CE
2
is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The output enable input is active LOW. With chip
enabled, when OE is Low and WE High, data will
be presented on the I/O pins. The I/O pins will be in
the high impedance state when OE is High.
*CE
2
is available on BGA package only.
CILETIV LESOM
Pin Descriptions
A4
A3
A2
A1
A0
CE
1
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Pin Configurations (Top View)
44-Pin TSOP-II (Standard)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UBE
LBE
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A17
48 BGA
1
A
B
C
D
E
F
G
H
2
3
4
5
6
A
B
1
BLE
I/O9
2
OE
BHE
3
A0
A3
4
A1
A4
A6
A7
5
A2
6
CE
2
CE
1
I/O1
I/O2 I/O3
I/O4 VCC
C I/O10 I/O11 A5
D
E
F
VSS I/O12 A17
VCC I/O13 NC
A16 I/O5 VSS
I/O15 I/O14 A14 A15 I/O6 I/O7
NC
A8
A12 A13
A9
WE
I/O8
NC
G I/O16
H
NC
A10 A11
Note:
NC means no connect.
TOP VIEW
TOP VIEW
V62C21164096 Rev. 1.6 October 2001
2
V62C21164096
CILETIV LESOM
V
MOSEL-VITELIC
MANUFACTURED
62 = STANDARD
Part Number Information
62
C
21
16
4096
–
TEMP.
SRAM
FAMILY
OPERATING
VOLTAGE
DENSITY
4096K
PWR.
70 ns
85 ns
T = TSOP STANDARD
B = BGA
L = LOW POWER
LL = DOUBLE LOW POWER
SPEED
PKG
BLANK = 0°C to 70°C
I = -40°C to +85°C
C = CMOS PROCESS
21 = 2.3V–3.0V
ORGANIZATION
16 = 16-bit
Absolute Maximum Ratings
(1)
Symbol
V
CC
V
N
V
DQ
T
BIAS
T
STG
Parameter
Supply Voltage
Input Voltage
Input/Output Voltage Applied
Temperature Under Bias
Storage Temperature
Commercial
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
V
CC
+ 0.3
-10 to +125
-55 to +125
Industrial
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
V
CC
+ 0.3
-65 to +135
-65 to +150
Units
V
V
V
°C
°C
NOTE:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance*
T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
I/O
= 0V
Max.
6
8
Unit
pF
pF
NOTE:
1. This parameter is guaranteed and not tested.
Truth Table
Mode
Standby
Standby
Output Disable
Output Disable
Read
Read
Read
Write
Write
Write
CE
1
H
X
L
L
L
L
L
L
L
L
CE
2
X
L
H
H
H
H
H
H
H
H
OE
X
X
X
H
L
L
L
X
X
X
WE
X
X
X
H
H
H
H
L
L
L
UBE
X
X
H
X
L
L
H
L
L
H
LBE
X
X
H
X
L
H
L
L
H
L
I/O
9-16
Operation
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
High Z
I/O
1-8
Operation
High Z
High Z
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
High Z
D
IN
NOTE:
X = Don’t Care, L = LOW, H = HIGH
V62C21164096 Rev. 1.6 October 2001
3
V62C21164096
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. V
IL
(Min.) = -3.0V for pulse width < 20ns.
3. Maximum values.
CILETIV LESOM
Symbol
V
IL
V
IH
I
IL
I
OL
V
OL
V
OH
DC Electrical Characteristics
(over all temperature ranges, V
CC
= 2.3V – 3.0V)
Parameter
Input LOW Voltage
(1,2)
Input HIGH Voltage
(1)
Input Leakage Current
Output Leakage Current
Output LOW Voltage
Output HIGH Voltage
V
CC
= Max, V
IN
= 0V to V
CC
V
CC
= Max, CE = V
IH
, V
OUT
= 0V to V
CC
V
CC
= Min, I
OL
= 2.1mA
V
CC
= Min, I
OH
= -0.5mA
Test Conditions
Min.
-0.3
2.0
-1
-1
—
V
CC
– 0.4
Typ.
—
—
—
—
—
—
Max.
0.4
V
CC
+ 0.3
1
1
0.4
—
Units
V
V
µA
µA
V
V
Symbol
I
CC1
Parameter
Average Operating Current, CE
1
= V
IL
, CE
2
= VCC – 0.2V, Output Open,
V
CC
= Max.
TTL Standby Current
CE
≥
V
IH
, V
CC
= Max., f = 0
CMOS Standby Current, CE
1
≥
V
CC
– 0.2V, CE
2
< 0.2V
V
IN
≥
V
CC
– 0.2V or V
IN
≤
0.2V, V
CC
= Max., f = 0
Power Com.
(3)
f = fmax
f = 1 MHz
L
LL
L
LL
35
4
0.5
0.3
10
4
Ind.
(3)
40
5
1
1
15
6
Units
mA
I
SB
mA
I
SB1
µA
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Timing Reference Levels
Output Load
0 to 2.0V
Key to Switching Waveforms
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
OUTPUTS
WILL BE
STEADY
WILL BE
CHANGING
FROM H TO L
WILL BE
CHANGING
FROM L TO H
CHANGING:
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
5 ns
1.1V
see below
AC Test Loads and Waveforms
MAY CHANGE
FROM L TO H
TTL
C
L
*
DON'T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
* Includes scope and jig capacitance
C
L
= 30 pF + 1 TTL Load
V62C21164096 Rev. 1.6 October 2001
4
V62C21164096
NOTES:
1. t
RC
= Read Cycle Time
2. T
A
= +25°C.
CILETIV LESOM
Symbol
V
DR
Data Retention Characteristics
Parameter
V
CC
for Data Retention
CE
1
≥
V
CC
– 0.2V, CE
2
< 0.2V, V
IN
≥
V
CC
– 0.2V,
or V
IN
≤
0.2V
Data Retention Current
CE
1
≥
V
DR
– 0.2V, CE
2
< 0.2V, V
IN
≥
V
CC
– 0.2V,
or V
IN
≤
0.2V, V
DR
= 1.2V
Com’l
L
LL
Ind.
L
LL
t
CDR
t
R
Chip Deselect to Data Retention Time
Operation Recovery Time (see Retention Waveform)
Power
Min.
1.2
Typ.
(2)
—
Max.
3.0
Units
V
I
CCDR
—
—
—
—
0
t
RC(1)
1
0.5
—
—
—
—
3
2
5
4
—
—
µA
ns
ns
Low V
CC
Data Retention Waveform (CE Controlled)
Data Retention Mode
V
CC
2.3V
t
CDR
CE
1
2.0V
CE
1
≥
V
CC
– 0.2V
V
DR
≥
1.2V
t
R
2.0V
2.3V
V62C21164096 Rev. 1.6 October 2001
5
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