models), all on one small monolithic chip. A combina-
tion of current-switch design techniques accomplishes
not only 15-bit monotonicity over the entire specified
temperature range, but also a maximum end-point
linearity error of
±0.0015%
of full-scale range. Total
full-scale gain drift is limited to
±10ppm/°C
maximum
(LH and CH grades).
Digital
Inputs
16-Bit
Ladder
Resistor
Network
And
Current
Switches
Reference
Circuit
Reference Output
Common
Summing Junction
Output
Voltage Models
Only
Gain Adjust
+V
CC
–V
CC
V
DD
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
At +25°C and rated power supplies, unless otherwise noted.
DAC702/703J
PARAMETER
INPUT
DIGITAL INPUT
Resolution
Digital Inputs
(1)
V
IH
V
IL
I
IH
, V
I
= +2.7V
I
IL
, V
I
= +0.4V
16
+2.4
–1.0
–0.35
+V
CC
+0.8
+40
–0.5
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Bits
V
V
µA
mA
MIN
TYP
MAX
DAC701/702/703K
MIN
TYP
MAX
DAC701/702/703B, S
MIN
TYP
MAX
DAC701/702/703L, C
MIN
TYP
MAX
UNITS
TRANSFER CHARACTERISTICS
ACCURACY
(2)
Linearity Error
(4)
Differential Linearity
Error
(4)
Differential Linearity
Error at Bipolar Zero
(DAC702/703)
(4)
Gain Error
(5)
Zero Error
(5, 6)
Monotonicity Over Spec.
Temp Range
DRIFT
(over specification
temperature range)
Total Error Over
Temperature Range
(all models)
(7)
Total Full Scale Drift:
DAC701
DAC702/703
Gain Drift (all models)
Zero Drift:
DAC701
DAC702/703
Differential Linearity
Over Temp.
(4)
Linearity Error
Over Temp.
(4)
SETTLING TIME
(to
±0.003%
of FSR)
(8)
DAC701/703 (V
OUT
Models)
Full Scale Step, 2kΩ Load
1LSB Step at
Worst-Case Code
(9)
Slew Rate
DAC702 (I
OUT
Models)
Full Scale Step (2mA),
10 to 100Ω Load
1kΩ Load
OUTPUT
VOLTAGE OUTPUT
MODELS
DAC701 (CSB Code)
DAC703 (COB Code)
Output Current
Output Impedance
Short Circuit to
Common Duration
CURRENT OUTPUT
MODELS
DAC702 (COB Code)
(10)
Output Impedance
(10)
Compliance Voltage
±0.0015
±0.003
±0.006
±0.012
T
T
±0.003
±0.006
T
T
T
T
±0.00075 ±0.0015
±0.0015
±0.003
% of FSR
(3)
% of FSR
±0.07
±0.05
13
±0.30
±0.10
14
±0.003
T
T
±0.006
±0.15
T
T
±0.0015
±0.05
T
±0.003
±0.10
T
15
T
T
T
T
T
T
% of FSR
%
% of FSR
Bits
±0.08
±10
±10
±10
T
T
T
T
±2.5
T
±0.15
±30
±25
±25
±5
±12
+0.009,
–0.006
±0.006
±0.05
±8.5
±7
±7
±1.5
±4
±0.10
±18
±15
±15
±3
±10
T
T
±6
T
±5
T
±2.5
T
±13
T
±10
T
±5
+0.006,
–0.003
±0.003
% of FSR
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
ppm of FSR/°C
ppm of FSR/°C
% of FSR
±30
±5
±15
±0.012
±0.012
T
% of FSR
4
2.5
10
T
T
T
8
T
T
T
T
T
T
T
T
µs
µs
V/µs
350
1
T
T
1000
3
T
T
T
T
T
T
T
T
ns
µs
±5
±10
T
0.15
Indefinite
0 to +10
T
T
T
T
T
T
T
T
T
T
T
T
V
V
mA
Ω
±1
2.45
±2.5
T
T
T
T
T
T
T
T
T
mA
kΩ
V
®
DAC701, 702, 703
2
SPECIFICATIONS
(CONT)
At +25°C and rated power supplies, unless otherwise noted.
DAC702/703J
PARAMETER
REFERENCE VOLTAGE
Voltage
Source Current Available
for External Loads
Temperature Coefficient
Short Circuit to Common
Duration
POWER SUPPLY REQUIREMENTS
Voltage: +V
CC
–V
CC
V
DD
Current (No Load):
DAC702
(I
OUT
Models)
+V
CC
–V
CC
V
DD
DAC701/703
(V
OUT
Models)
+V
CC
–V
CC
V
DD
Power Dissipation:
(V
DD
= +5.0V)
(11)
DAC702
DAC701/703
Power Supply Rejection:
+V
CC
–V
CC
V
DD
TEMPERATURE RANGE
Specification:
B, C Grades
S Grades
J, K, L Grades
Storage: Ceramic
Plastic, SOIC
–25
–55
0
–60
+70
+100
T
–60
T
T
+150
T
T
+85
+125
T
T
0
T
T
+70
T
°C
°C
°C
°C
°C
13.5
13.5
+4.5
15
15
+5
16.5
16.5
+16.5
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
V
V
V
MIN
TYP
+6.3
+2.5
±10
Indefinite
MAX
DAC701/702/703K
MIN
+6.0
+1.5
TYP
+6.3
T
T
T
MAX
+6.6
DAC701/702/703B, S
MIN
+6.24
T
±25
TYP
+6.3
T
T
T
MAX
+6.36
DAC701/702/703L, C
MIN
T
T
±15
TYP
T
T
T
T
MAX
T
UNITS
V
mA
ppm/°C
T
+10
–13
+4
+25
–25
+8
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
mA
mA
mA
+16
–18
+4
+30
–30
+8
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
mA
mA
mA
365
530
±0.0015
±0.0015
±0.0001
±0.006
±0.006
±0.001
T
T
T
T
T
790
940
T
T
T
T
T
T
T
T
630
780
±0.003
±0.003
T
T
T
T
T
T
T
T
T
T
T
mW
mW
% of FSR/%V
CC
% of FSR/%V
CC
% of FSR/%V
DD
T
Specification same as model to the left.
NOTES: (1) Digital inputs are TTL, LSTTL, 54/74C, 54/74HC, and 54/74HTC compatible over the operating voltage range of V
DD
= +5V to +15V and over the specified
temperature range. The input switching threshold remains at the TTL threshold of 1.4V over the supply range of V
DD
= +5V to +15V. As logic “0” and logic “1” inputs vary over
0V to +0.8V and +2.4V to +10V respectively, the change in the D/A converter output voltage will not exceed
±0.0015%
of FSR for the LH and CH grades,
±0.003%
of FSR for
the BH grade and
±0.006%
of FSR for the KG grade. (2) DAC702 (current-output models) is specified and tested with an external output operational amplifier connected using
the internal feedback resistor in all parameters except settling time. (3) FSR means full-scale range and is 20V for the
±10V
range (DAC703), 10V for the 0 to +10V range
(DAC701). FSR is 2mA for the
±1mA
range (DAC702). (4)
±0.0015%
of full-scale range is equivalent to 1LSB in 15-bit resolution.
±0.003%
of full-scale range is equivalent to
1LSB in 14-bit resolution.
±0.006%
of full-scale range is equivalent to 1LSB in 13-bit resolution. (5) Adjustable to zero with external trim potentiometer. Adjusting the gain
potentiometer rotates the transfer function around the zero point. (6) Error at input code FFFF
H
for DAC701, 7FFF
H
for DAC702 and DAC703. (7) With gain and zero errors
adjusted to zero at +25°C. (8) Maximum represents the 3σ limit. Not 100% tested for this parameter. (9) At the major carry, 7FFF
H
to 8000
H
and 8000
H
to 7FFF
H
. (10) Tolerance
on output impedance and output current is
±30%.
(11) Power dissipation is an additional 40mW when V
DD
is operated at +15V.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN
product for use in life support devices and/or systems.
®
3
DAC701, 702, 703
CONNECTION DIAGRAMS
MSB
1
2
3
4
5
Digital
Inputs
6
7
8
9
10
11
12
16-Bit
Ladder
Resistor
Network
and
Current
Switches
Reference
Circuit
24
23
(2)
+V
CC
270kΩ
(3)
22
0.0022µF
21
20
R
F
(4)
3.9MΩ
(3)
19
(2)
–V
CC
18
17
LSB
Voltage Models
Only
(2)
V
DD (1)
16
15
14
13
Digital
Inputs
NOTES: (1) Can be tied to +V
CC
instead of having
separate V
DD
supply. (2) Decoupling capacitors are
0.1µF to 1.0µF. (3) Potentiometers are 10kΩ to
100kΩ. (4) 5kΩ (DAC701), 10kΩ (DAC702/703).
PIN ASSIGNMENTS
ALL PACKAGES
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DAC702
Bit 1 (MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16 (LSB)
R
FEEDBACK
V
DD
–V
CC
Common
I
OUT
Gain Adjust
+V
CC
+6.3V Reference Output
DAC701/703
Bit 1 (MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16 (LSB)
V
OUT
V
DD
–V
CC
Common
Summing Junction (Zero Adjust)
Gain Adjust
+V
CC
+6.3V Reference Output
ABSOLUTE MAXIMUM RATINGS
(1)
+V
CC
to Common ........................................................................ 0V, +18V
–V
CC
to Common ........................................................................ 0V, –18V
V
DD
to Common .......................................................................... 0V, +18V
Digital Data Inputs to Common ................................................ –1V, +18V
Reference Out to Common ........................... Indefinite Short to Common
京公网安备 11010802033920号
EEWORLD
