1. Features
•
MPEGI/II-Layer 3 Hardwired Decoder
– Stand-alone MP3 decoder
– 48, 44.1, 32, 24, 22.05, 16 KHz sampling freq.
– Separated digital volume control on left and right channels (software control using
31 steps)
– Bass, medium, and Treble Control (31 steps)
– Bass Boost sound effect.
– Ancillary data extraction
– “CRC Error” and “MPEG Frame Synchronization” indicators
Programmable Audio Output for interfacing with common audio DAC available on the
market
– PCM format compatible
– I
2
S format compatible
8-bit MCU C51 core based (F
MAX
= 20 MHz)
2304 bytes of Internal RAM
64 Kbytes of Code Memory
– FLASH: T89C51SND1, ROM: T83C51SND1
4 Kbytes of Boot Flash Memory (T89C51SND1)
– ISP: download from USB or UART to any external memory cards
USB Rev 1.1 controller
– “Full speed” data transmission
Built-in PLL
– MP3 Audio clocks
– USB clock
MultiMediaCard Interface Compatibility
Atmel DataFlash SPI Interface Compatibility
IDE/ATAPI Interface
2 Channels 10-bit ADC, 8KHz (8 true bit)
– Battery voltage Monitoring
– Voice recording controlled by software
Up to 44 bits of General Purpose I/Os for:
– 4-bit interrupt keyboard port for a 4 x n matrix
– Smartmedia software interface
Standard Two 16-bit Timers/Counters
Hardware Watchdog Timer
Standard Full Duplex UART with Baud Rate Generator
2-wire Master and Slave Modes Controller
SPI Master and Slave Modes Controller
Power Management
– Power-On reset
– Software programmable MCU clock
– Idle mode, Power-Down mode
Operating conditions:
– 3V,
±10%,
25 mA typical operating at 25°C
– -40°C to +85°C
Packages
– TQFP80, PLCC84 (development board)
– Dice
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Single Chip
Microcontroller
with MP3
Decoder and
Man Machine
Interface
T8xC51SND1
•
•
Rev. D – 15-Nov-01
1
2. Description
The T8xC51SND1 product is a fully integrated stand-alone hardwired MPEGI/II-Layer 3
decoder with a C51 microcontroller core handling data flow and MP3-player control.
The T89C51SND1 includes 64 Kbytes of FLASH memory and allows In System Pro-
gramming through an embedded 4 Kbytes of Boot FLASH Memory.
The T83C51SND1 includes 64 Kbytes of ROM memory.
The T8xC51SND1 includes 2304 bytes of RAM memory.
The T8xC51SND1 provides all necessary features for man machine interface like tim-
ers, keyboard port, serial or parallel interface (USB, 2-wire, SPI, IDE), ADC input, I
2
S
output, and all external memory interface (NAND or NOR FLASH, SmartMedia,
MultiMedia).
3. Typical Applications
•
•
•
•
MP3-Player
PDA, Camera, Mobile Phone MP3
Car Audio/Multimedia MP3
Home Audio/Multimedia MP3
2
T8xC51SND1
Rev. D – 15-Nov-01
T8xC51SND1
4. Pin Description
4.1 Pinouts
Figure 1.
T8xC51SND1 80-pin QFP Package
P5.1
P5.0
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
VSS
VDD
P0.6/AD6
P0.7/AD7
P4.3/SS#
P4.2/SCK
P4.1/MOSI
P4.0/MISO
P2.0/A8
P2.1/A9
P4.7
P4.6
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
ALE
ISP#
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.6/SCL
P1.7/SDA
VDD
PVDD
FILT
PVSS
VSS
X2
X1
TST#
UVDD
UVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
T89C51SND1-RO (FLASH)
T83C51SND1-RO (ROM)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P4.5
P4.4
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
VSS
VDD
MCLK
MDAT
MCMD
RST
SCLK
DSEL
DCLK
DOUT
VSS
VDD
D+
D-
VDD
VSS
P3.0/RXD
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
P3.6/WR#
P3.7/RD#
AVDD
AVSS
AREFP
AREFN
AIN0
AIN1
P5.2
P5.3
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
3
Rev. D – 15-Nov-01
Figure 2.
T8xC51SND1 84-pin PLCC Package
NC
P5.1
P5.0
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
VSS
VDD
P0.6/AD6
P0.7/AD7
P4.3/SS#
P4.2/SCK
P4.1/MOSI
P4.0/MISO
P2.0/A8
P2.1/A9
P4.7
P4.6
ALE
ISP#
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.6/SCL
P1.7/SDA
VDD
PAVDD
FILT
PAVSS
VSS
X2
NC
X1
TST#
UVDD
UVSS
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
T89C51SND1-SR (FLASH)
NC
P4.5
P4.4
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
VSS
VDD
MCLK
MDAT
MCMD
RST
SCLK
DSEL
DCLK
DOUT
VSS
VDD
4.2 Signals
All the T8xC51SND1 signals are detailed by functionality in Table 1 to Table 14.
Table 1.
Ports Signal Description
Signal
Name
Type
Description
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. To
avoid any parasitic current consumption, floating P0 inputs must be
polarized to V
DD
or V
SS
.
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
Alternate
Function
P0.7:0
I/O
D+
D-
VDD
VSS
P3.0/RXD
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
P3.6/WR#
P3.7/RD#
AVDD
AVSS
AREFP
AREFN
AIN0
AIN1
P5.2
P5.3
NC
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
AD7:0
P1.7:0
I/O
KIN3:0
SCL
SDA
4
T8xC51SND1
Rev. D – 15-Nov-01
T8xC51SND1
Signal
Name
P2.7:0
Alternate
Function
A15:8
RXD
TXD
P3.7:0
I/O
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
INT0#
INT1#
T0
T1
WR#
RD#
MISO
MOSI
SCK
SS#
-
Type
I/O
Description
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
P4.7:0
I/O
Port 4
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
P5.3:0
I/O
Port 5
P5 is a 4-bit bidirectional I/O port with internal pull-ups.
Table 2.
Clock Signal Description
Signal
Name
Type
Description
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, its output is connected to this
pin. X1 is the clock source for internal timing.
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, leave X2 unconnected.
PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter.
Alternate
Function
X1
I
-
X2
O
-
FILT
I
-
Table 3.
Timer 0 and Timer 1 Signal Description
Signal
Name
Type
Description
Timer 0 Gate Input
INT0# serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
INT0#
I
External Interrupt 0
INT0# input sets IE0 in the TCON register. If bit IT0 in this register is
set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0
is set by a low level on INT0#.
Timer 1 Gate Input
INT1# serves as external run control for timer 1, when selected by
GATE1 bit in TCON register.
INT1#
I
External Interrupt 1
INT1# input sets IE1 in the TCON register. If bit IT1 in this register is
set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1
is set by a low level on INT1#.
P3.3
P3.2
Alternate
Function
5
Rev. D – 15-Nov-01
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