BSI
n
FEATURES
Ultra Low Power/High Speed CMOS SRAM
512K X 16 bit
n
DESCRIPTION
BH616UV8010
Ÿ
Wide V
CC
low operation voltage : 1.65V ~ 3.6V
Ÿ
Ultra low power consumption :
V
CC
= 3.0V
Operation current : 5.0mA at 70ns at 25
O
C
1.5mA at 1MHz at 25
O
C
Standby current : 2.5uA at 25
O
C
V
CC
= 2.0V
Data retention current : 2.5uA at 25
O
C
Ÿ
High speed access time :
-70
70ns at 1.8V at 85
O
C
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE1, CE2 and OE options
Ÿ
I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation, no clock, no refreash
Ÿ
Data retention supply voltage as low as 1.0V
The BH616UV8010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 by 16 bits and operates
in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25
O
C and maximum access time of 70ns at 1.8V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH616UV8010 is available in DICE form, JEDEC standard 48-pin
TSOP-I and 48-ball BGA package.
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PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
V
CC
RANGE
SPEED
(ns)
V
CC
=1.8~3.6V
POWER CONSUMPTION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.6V V
CC
=1.8V V
CC
=3.6V V
CC
=1.8V
BH616UV8010DI
BH616UV8010TI
BH616UV8010AI
+0
O
C to +70
O
C
1.65V ~ 3.6V
-25
O
C to +85
O
C
70
13uA
10uA
10mA
7mA
DICE
TSOP1-48
70
15uA
12uA
10mA
7mA
BGA-48-0608
n
PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
A
B
C
D
E
F
G
H
LB
DQ8
DQ9
VSS
VCC
DQ14
DQ15
A18
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
5
A2
CE1
DQ1
DQ3
DQ4
DQ5
WE
A11
6
CE2
DQ0
DQ2
VCC
VSS
DQ6
DQ7
NC
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE1
A0
n
BLOCK DIAGRAM
BH616UV8010TC
BH616UV8010TI
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 8192
8192
DQ0
.
.
.
.
.
.
DQ15
.
.
.
.
.
.
16
Data
Input
Buffer
Data
Output
Buffer
16
512
Column Decoder
9
Address Input Buffer
Control
16
Column I/O
Write Driver
Sense Amp
16
2
OE
UB
DQ10
DQ11
DQ12
DQ13
NC
A8
3
A0
A3
A5
A17
VSS
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
CE2
CE1
WE
OE
UB
LB
V
CC
V
SS
A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV8010
1
Revision 1.0
Jul.
2005
BSI
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PIN DESCRIPTIONS
BH616UV8010
Function
These 19 address inputs select one of the 524,288 x 16 bit in the RAM
Name
A0-A18 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
DQ0-DQ15 Data Input/Output
Ports
V
CC
V
SS
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n
TRUTH TABLE
MODE
Chip De-selected
(Power Down)
CE1
H
X
X
CE2
X
L
X
H
WE
X
X
X
H
OE
X
X
X
H
LB
X
X
H
X
L
UB
X
X
H
X
L
L
H
L
L
H
DQ0~DQ7 DQ8~DQ15 V
CC
CURRENT
High Z
High Z
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
X
D
IN
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
X
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
Output Disabled
L
Read
L
H
H
L
H
L
L
Write
L
H
L
X
H
L
NOTES: H means V
IH
; L means V
IL
; X means don’t care (Must be V
IH
or V
IL
state)
R0201-BH616UV8010
2
Revision 1.0
Jul.
2005
BSI
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ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
(1)
BH616UV8010
n
OPERATING RANGE
UNITS
V
O
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
to 4.6V
-40 to +125
-60 to +150
1.0
20
RANG
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to + 70
O
C
-25
O
C to + 85
O
C
V
CC
1.65V ~ 3.6V
1.65V ~ 3.6V
C
C
W
mA
n
CAPACITANCE
(1)
(T
A
= 25 C, f = 1.0MHz)
MAX.
UNITS
pF
pF
O
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
2.
–2.0V
in case of AC pulse width less than 30 ns
O
O
SYMBOL PAMAMETER CONDITIONS
C
IN
Input
V
IN
= 0V
6
Capacitance
Input/Output
C
IO
V
I/O
= 0V
8
Capacitance
1. This parameter is guaranteed and not 100% tested.
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DC ELECTRICAL CHARACTERISTICS (T
A
= -25 C to +85 C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
PARAMETER
Power Supply
V
CC
=1.8V
V
CC
=3.6V
TEST CONDITIONS
MIN.
1.65
-0.3
(2)
1.4
2.0
--
TYP.
(1)
--
MAX.
3.6
0.4
0.8
UNITS
V
Input Low Voltage
--
V
Input High Voltage
V
IN
= 0V to V
CC
,
CE1 = V
IH
or CE2 = V
IL
V
I/O
= 0V to V
CC
,
V
CC
=1.8V
V
CC
=3.6V
--
V
CC
+0.3
(3)
V
Input Leakage Current
--
1
uA
I
LO
Output Leakage Current
CE1 = V
IH
or CE2 = V
IL
or OE = V
IH
or
UB = LB = V
IH
V
CC
= Max, I
OL
= 0.2mA
V
CC
= Max, I
OL
= 2.0mA
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
--
--
1
0.2
0.4
uA
V
OL
V
OH
I
CC
I
CC1
I
CCSB
I
CCSB1
(5)
Output Low Voltage
--
V
CC
-0.2
2.4
--
--
V
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current
–
TTL
V
CC
= Min, I
OH
= -0.1mA
V
CC
= Min, I
OH
= -1.0mA
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = F
MAX(4)
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = 1MHz
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
--
4.5
5.0
--
7
10
1.5
2.0
0.5
1.0
V
mA
--
1.0
1.5
mA
--
--
2.5
2.5
mA
Standby Current
–
CMOS
--
12
15
uA
1. Typical characteristics are at T
A
=25
O
C.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
5. I
CCSB1(MAX.)
is 10uA/13uA at V
CC
=1.8V/3.6V and T
A
=0
O
C ~ 70
O
C.
R0201-BH616UV8010
Revision 1.0
Jul.
2005
3
BSI
n
DATA RETENTION CHARACTERISTICS (T
A
= -25 C to +85 C)
SYMBOL
V
DR
I
CCDR
(3)
BH616UV8010
O
O
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
V
CC
=1.0V
V
CC
=2.0V
MIN.
1.0
--
0
TYP.
(1)
--
0.5
2.5
--
--
MAX.
--
3.0
12
--
--
UNITS
V
uA
ns
ns
t
CDR
t
R
See Retention Waveform
t
RC (2)
1. T
A
=25
O
C.
2. t
RC
= Read Cycle Time.
3. I
CCDR(MAX.)
is 2.5uA /10uA at V
CC
=1.0V/2.0V and T
A
=0
O
C ~ 70
O
C.
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
CC
V
IH
V
CC
V
DR
≧1.0V
V
CC
t
CDR
CE1≧V
CC
- 0.2V
t
R
V
IH
CE1
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
CC
V
DR
≧1.0V
V
CC
V
CC
t
CDR
t
R
CE2≦0.2V
CE2
V
IL
V
IL
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
t
CLZ1
, t
CLZ2
, t
BE
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
BDO
, t
OHZ
, t
WHZ
, t
OW
Output Load
Others
V
CC
/ 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
ALL INPUT PULSES
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BH616UV8010
4
Revision 1.0
Jul.
2005
BSI
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -25 C to +85 C)
READ CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
O
O
BH616UV8010
CYCLE TIME : 70ns
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
Data Byte Control to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
(CE1)
(CE2)
(LB, UB)
(CE1)
(CE2)
(LB, UB)
(CE1)
(CE2)
(LB, UB)
MIN.
70
--
--
--
--
--
10
10
10
5
--
--
--
--
10
TYP.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
MAX.
--
70
70
70
70
30
--
--
--
--
25
25
25
25
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQX
t
E1LQV
t
E2LQV
t
BLQV
t
GLQV
t
E1LQX
t
E2LQX
t
BLQX
t
GLQX
t
E1HQZ
t
E2HQZ
t
BHQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS1
t
ACS2
t
BA
t
OE
t
CLZ1
t
CLZ2
t
BE
t
OLZ
t
CHZ1
t
CHZ2
t
BDO
t
OHZ
t
OH
n
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
t
OH
R0201-BH616UV8010
5
Revision 1.0
Jul.
2005
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