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BH616UV8010TI

Description
Ultra Low Power/High Speed CMOS SRAM 512K X 16 bit
File Size140KB,11 Pages
ManufacturerBSI
Websitehttp://www.brilliancesemi.com/
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BH616UV8010TI Overview

Ultra Low Power/High Speed CMOS SRAM 512K X 16 bit

BSI
n
FEATURES
Ultra Low Power/High Speed CMOS SRAM
512K X 16 bit
n
DESCRIPTION
BH616UV8010
Ÿ
Wide V
CC
low operation voltage : 1.65V ~ 3.6V
Ÿ
Ultra low power consumption :
V
CC
= 3.0V
Operation current : 5.0mA at 70ns at 25
O
C
1.5mA at 1MHz at 25
O
C
Standby current : 2.5uA at 25
O
C
V
CC
= 2.0V
Data retention current : 2.5uA at 25
O
C
Ÿ
High speed access time :
-70
70ns at 1.8V at 85
O
C
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE1, CE2 and OE options
Ÿ
I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation, no clock, no refreash
Ÿ
Data retention supply voltage as low as 1.0V
The BH616UV8010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 by 16 bits and operates
in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25
O
C and maximum access time of 70ns at 1.8V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH616UV8010 is available in DICE form, JEDEC standard 48-pin
TSOP-I and 48-ball BGA package.
n
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
V
CC
RANGE
SPEED
(ns)
V
CC
=1.8~3.6V
POWER CONSUMPTION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.6V V
CC
=1.8V V
CC
=3.6V V
CC
=1.8V
BH616UV8010DI
BH616UV8010TI
BH616UV8010AI
+0
O
C to +70
O
C
1.65V ~ 3.6V
-25
O
C to +85
O
C
70
13uA
10uA
10mA
7mA
DICE
TSOP1-48
70
15uA
12uA
10mA
7mA
BGA-48-0608
n
PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
A
B
C
D
E
F
G
H
LB
DQ8
DQ9
VSS
VCC
DQ14
DQ15
A18
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
5
A2
CE1
DQ1
DQ3
DQ4
DQ5
WE
A11
6
CE2
DQ0
DQ2
VCC
VSS
DQ6
DQ7
NC
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE1
A0
n
BLOCK DIAGRAM
BH616UV8010TC
BH616UV8010TI
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 8192
8192
DQ0
.
.
.
.
.
.
DQ15
.
.
.
.
.
.
16
Data
Input
Buffer
Data
Output
Buffer
16
512
Column Decoder
9
Address Input Buffer
Control
16
Column I/O
Write Driver
Sense Amp
16
2
OE
UB
DQ10
DQ11
DQ12
DQ13
NC
A8
3
A0
A3
A5
A17
VSS
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
CE2
CE1
WE
OE
UB
LB
V
CC
V
SS
A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV8010
1
Revision 1.0
Jul.
2005

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