Chapter 3. JTAG & In-System
Programmability
MII51003-1.1
IEEE Std. 1149.1
(JTAG) Boundary
Scan Support
All MAX
®
II devices provide Joint Test Action Group (JTAG) boundary-
scan test (BST) circuitry that complies with the IEEE Std. 1149.1-2001
specification. JTAG boundary-scan testing can only be performed at any
time after V
CCINT
and all V
CCIO
banks have been fully powered and a
t
CONFIG
amount of time has passed. MAX II devices can also use the JTAG
port for in-system programming together with either the Quartus
®
II
software or hardware using Programming Object Files (.pof), Jam
TM
Standard Test and Programming Language (STAPL) Files (.jam) or Jam
Byte-Code Files (.jbc).
The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The
supported voltage level and standard is determined by the V
CCIO
of the
bank where it resides. The dedicated JTAG pins reside in Bank 1 of all
MAX II devices.
MAX II devices support the JTAG instructions shown in
Table 3–1.
Table 3–1. MAX II JTAG Instructions (Part 1 of 2)
JTAG Instruction
SAMPLE/PRELOAD
Instruction Code
00 0000 0101
Description
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation, and permits an
initial data pattern to be output at the device pins.
Allows the external circuitry and board-level interconnects to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation.
Selects the 32-bit
USERCODE
register and places it between
the
TDI
and
TDO
pins, allowing the
USERCODE
to be serially
shifted out of
TDO.
This register defaults to all 1’s if not
specified in the Quartus II software.
Selects the
IDCODE
register and places it between
TDI
and
TDO,
allowing the IDCODE to be serially shifted out of
TDO.
EXTEST
(1)
00 0000 1111
BYPASS
11 1111 1111
USERCODE
00 0000 0111
IDCODE
00 0000 0110
Altera Corporation
June 2004
Core Version a.b.c variable
3–1
Preliminary
IEEE Std. 1149.1 (JTAG) Boundary Scan Support
Table 3–1. MAX II JTAG Instructions (Part 2 of 2)
JTAG Instruction
HIGHZ
(1)
Instruction Code
00 0000 1011
Description
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation, while tri-stating all of the I/O
pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation, while holding I/O pins to a
state defined by the data in the boundary-scan register.
This instruction allows the user to define their own scan chain
between
TDI
and
TDO
in the MAX II logic array. This
instruction is also used for custom logic and JTAG interfaces.
This instruction allows the user to define their own scan chain
between
TDI
and
TDO
in the MAX II logic array. This
instruction is also used for custom logic and JTAG interfaces.
IEEE 1532 ISC instructions used when programming a MAX II
device via the JTAG port.
CLAMP
(1)
00 0000 1010
USER0
00 0000 1100
USER1
00 0000 1110
IEEE 1532 instructions
(2)
Notes to
Table 3–1:
(1)
(2)
HIGHZ, CLAMP,
and
EXTEST
instructions do not disable weak pull-up resistors or bus hold features.
These instructions are shown in the 1532 BSDL files, which will be posted on the Altera
®
web site at
www.altera.com
when they are available.
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June 2004
JTAG & In-System Programmability
The MAX II device instruction register length is 10 bits and the
USERCODE
register length is 32 bits.
Tables 3–2
and
3–3
show the boundary-scan
register length and device
IDCODE
information for MAX II devices.
Table 3–2. MAX II Boundary-Scan Register Length
Device
EPM240
EPM570
EPM1270
EPM2210
Boundary-Scan Register Length
240
480
636
816
Table 3–3. 32-Bit MAX II Device IDCODE
Binary IDCODE (32 Bits)
(1)
Device
EPM240
EPM570
EPM1270
EPM2210
Version
(4 Bits)
0000
0000
0000
0000
Part Number
0010 0000 1010 0001
0010 0000 1010 0010
0010 0000 1010 0011
0010 0000 1010 0100
Manufacturer
Identity (11 Bits)
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
LSB
(1 Bit)
(2)
1
1
1
1
HEX IDCODE
0x020A10DD
0x020A20DD
0x020A30DD
0x020A40DD
Notes to
Table 3–2:
(1)
(2)
The most significant bit (MSB) is on the left.
The IDCODE's least significant bit (LSB) is always
1.
f
For JTAG AC characteristics, refer to the chapter on
DC & Switching
Characteristics.
For more information on JTAG BST, see the chapter on
IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices.
JTAG Translator
The JTAG translator feature allows you to access the JTAG TAP and state
signals when either the
USER0
or
USER1
instruction is issued to the JTAG
TAP. The
USER0
and
USER1
instructions bring the JTAG boundary scan
chain (TDI) through the user logic instead of the MAX II device’s
boundary scan cells. Each
USER
instruction allows for one unique user-
defined JTAG chain into the logic array.
Altera Corporation
June 2004
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MAX II Device Handbook, Volume 1
In System Programmability
General-Purpose Flash Loader
The JTAG translator ability to interface JTAG to non-JTAG devices is ideal
for general-purpose flash memory devices (such as Intel or Fujitsu based
devices) that require programming during in-circuit test. The flash
memory devices can be used for FPGA configuration or be part of system
memory. In many cases, the MAX II device is already connected to these
devices as the configuration control logic between the FPGA and the flash
device. Unlike ISP-capable CPLD devices, bulk flash devices do not have
JTAG TAP pins or connections. For small flash devices, it is common to
use the serial JTAG scan chain of a connected device to program the non-
JTAG flash device. This is slow and inefficient in most cases and
impractical for large parallel flash devices. Using the MAX II device’s
JTAG translator as a general-purpose flash loader to program and verify
flash contents provides a fast and cost-effective means of in-circuit
programming during test.
Figure 3–1
shows MAX II being used as a
general-purpose flash loader.
Figure 3–1. MAX II JTAG Translator as General-Purpose Flash Loader
MAX II Device
Flash
Memory Device
DQ[7..0]
A[20..0]
OE
WE
CE
RY/BY
TDO_U
TDI_U
TMS_U
TCK_U
SHIFT_U
CLKDR_U
UPDATE_U
RUNIDLE_U
USER1_U
DQ[7..0]
A[20..0]
OE
WE
CE
RY/BY
General-
Purpose
Flash Loader
Logic
(1), (2)
TDI
TMS
TCK
TDO
Notes to
Figure 3–1:
(1)
(2)
This block is implemented in LEs.
This function will be supported in a future version of the Quartus II software.
In System
Programmability
MAX II devices can be programmed in-system via the industry standard
4-pin IEEE Std. 1149.1 (JTAG) interface. In system programmability (ISP)
offers quick, efficient iterations during design development and
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Altera Corporation
June 2004
JTAG & In-System Programmability
debugging cycles. The logic, circuitry, and interconnects in the MAX II
architecture are configured with flash-based SRAM configuration
elements. These SRAM elements require configuration data to be loaded
each time the device is powered. The process of loading the SRAM data
is called configuration. The on-chip configuration flash memory (CFM)
block stores the SRAM element’s configuration data. The CFM block
stores the design’s configuration pattern in a reprogrammable flash array.
During ISP, the MAX II JTAG and ISP circuitry programs the design
pattern into the CFM block’s non-volatile flash array.
The MAX II JTAG and ISP controller internally generate the high
programming voltages required to program the CFM cells, allowing in-
system programming with any of the recommended operating external
voltage supplies (i.e., 3.3 V/2.5 V or 1.8 V for the MAX II devices with a
“G” ordering code). ISP can be performed anytime after V
CCINT
and all
V
CCIO
banks have been fully powered and the device has completed the
configuration power-up time. By default, during in-system
programming, the I/O pins are tri-stated and weakly pulled-up to V
CCIO
to eliminate board conflicts. The pull-up value ranges from 5 to 40 kΩ.
There are two other options in MAX II devices that allow user control of
I/O state or behavior during ISP.
f
For more information, refer to
“In-System Programming Clamp” on
page 3–8
and
“Real-Time ISP” on page 3–8.
These devices also offer an
ISP_DONE
bit that provides safe operation
when in-system programming is interrupted. This
ISP_DONE
bit, which
is the last bit programmed, prevents all I/O pins from driving until the
bit is programmed.
IEEE 1532 Support
The JTAG circuitry and ISP instruction set in MAX II devices is compliant
to the IEEE 1532-2002 programming specification. This provides
industry-standard hardware and software for in-system programming
among multiple vendor programmable logic devices (PLDs) in a JTAG
chain.
The MAX II 1532 BSDL files will be released on the Altera web site when
available.
Altera Corporation
June 2004
Core Version a.b.c variable
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MAX II Device Handbook, Volume 1
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