HCF4026B
DECADE COUNTER/DIVIDER WITH DECODED
7-SEGMENT DISPLAY OUTPUT AND DISPLAY ENABLE
s
s
s
s
s
s
s
s
s
s
COUNTER AND 7-SEGMENT DECODING IN
ONE PACKAGE
EASILY INTERFACED WITH 7-SEGMENT
DISPLAY TYPES
FULLY STATIC COUNTER OPERATION : DC
TO 6MHz (Typ.) AT V
DD
= 10V
IDEAL FOR LOW POWER DISPLAYS
DISPLAY ENABLE OUTPUT
QUIESCENT CURRENT SPECIF. UP TO 20V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DIP
SOP
ORDER CODES
PACKAGE
DIP
SOP
TUBE
HCF4026BEY
HCF4026BM1
T&R
HCF4026M013TR
DESCRIPTION
The HCF4026B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4026B consists of a 5-stages Johnson
decade counter and an output decoder which
converts the Johnson code to a 7 segment
decoded output for driving one stage in a
numerical display. This device is particularly
advantageous in display applications where low
power dissipation and/or low package count are
PIN CONNECTION
important. This device has CLOCK, RESET,
CLOCK INHIBIT, DISPLAY ENABLE input and
CARRY OUT, DISPLAY ENABLE, UNGATED "C"
SEGMENT and 7 DECODED outputs (a to g).
A high RESET signal clears the decade counter to
its zero count. The counter is advanced one count
at the positive clock signal transition if the CLOCK
INHIBIT signal is low. Counter advancement via
the clock line is inhibited when the CLOCK
INHIBIT signal is high. Antilock gating is provided
on the JOHNSON counter, thus assuring proper
counting sequence. The CARRY-OUT (C
OUT
)
signal completes one cycle every ten CLOCK
INPUT cycles and is used to clock the succeeding
decade directly in a multi-decade counting chain.
September 2001
1/11
HCF4026B
The seven decoded outputs (a, b, c, d, e, f, g)
illuminate the proper segments in a seven
segment display device used for representing the
decimal numbers 0 to 9. The 7-segment outputs
go high when the DISPLAY ENABLE IN is high.
When the DISPLAY ENABLE IN is low the seven
decoded outputs are forced low regardless of the
state of the counter. Activation of the display only
IINPUT EQUIVALENT CIRCUIT
when required results in significant power savings.
This system also facilitates implementation of
display character multiplexing. The CARRY OUT
and UNGATED "C" SEGMENT signals are not
gated by the DISPLAY ENABLE and therefore are
available continuously. This feature is a
requirement in implementation of certain divider
function such a as divide by 60 and divide by 12.
PIN DESCRIPTION
PIN No
1
10, 12, 13, 9,
11, 6, 7
2
15
3
5
4
SYMBOL
CLOCK
a to g
CLOCK
INHIBIT
RESET
DISPLAY
ENABLE IN
CARRY OUT
DISPLAY
ENABLE
OUT
UNGATED
"C" SEG-
MENT OUT
V
SS
V
DD
NAME AND FUNCTION
Clock Input
7 - Segments Decoded
Outputs
Clock Inhibit Input
Reset Input
Display Enable Input
Carry Out Output
Display Enable Output
Ungated "C" Segment
Output
Negative Supply Voltage
Positive Supply Voltage
14
8
16
FUNCTIONAL DIAGRAM
2/11
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