CAT93C46R
1-Kb Microwire Serial EEPROM
FEATURES
I
High speed operation: 4MHz @ 5V, 2MHz @ 1.8V
I
1.8V to 5.5V supply voltage range
I
Selectable x8 or x16 memory organization
I
Sequential read
I
Software write protection
I
Power-up inadvertent write protection
I
Low power CMOS technology
I
1,000,000 program/erase cycles
I
100 year data retention
I
Industrial temperature range
I
RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
DESCRIPTION
The CAT93C46R is a 1-Kb CMOS Serial EEPROM
device which is organized as either 64 registers of
16 bits or 128 registers of 8 bits, as determined by the
state of the ORG pin. The CAT93C46R features
sequential read and self-timed internal write with auto-
clear. On-chip Power-On Reset circuitry protects the
internal logic against powering up in the wrong state.
In contrast to the CAT93C46, the CAT93C46R features
an internal instruction clock counter which provides
improved noise immunity for Write/Erase commands.
8-pad TDFN packages
PIN CONFIGURATION
PDIP (L)
SOIC (V, X)
TSSOP (Y)
TDFN (VP2)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
NC
VCC
CS
SK
FUNCTIONAL SYMBOL
V
CC
SOIC (W)
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
ORG
CS
SK
DI
CAT93C46R
DO
GND
PIN FUNCTIONS
Pin Name
CS
SK
DI
DO
V
CC
GND
ORG
NC
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
For Ordering Information details, see page 12.
Note: When the ORG pin is connected to V
CC
, the x16 organization
is selected. When it is connected to ground, the x8 pin is selected.
If the ORG pin is left unconnected, then an internal pull-up device
will select the x16 organization.
* The Green & Gold seal identifies RoHS-compliant packaging, using NiPdAu
pre-plated lead frames.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1107, Rev. F
CAT93C46R
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
-65°C to +150°C
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than V
CC
+1.5V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Block Mode, V
CC
= 5V, T
A
= 25°C.
Parameter
Power Supply Current
(Write)
Power Supply Current
(Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1MHz
V
CC
= 5.0V
f
SK
= 1MHz
V
CC
= 5.0V
CS = 0V
ORG = GND
CS = 0V
ORG = Float or V
CC
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
4.5V
≤
V
CC
< 5.5V
4.5V
≤
V
CC
< 5.5V
1.8V
≤
V
CC
< 4.5V
1.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
< 5.5V
I
OL
= 2.1mA
4.5V
≤
V
CC
< 5.5V
I
OH
= -400µA
1.8V
≤
V
CC
< 4.5V
I
OL
= 1mA
1.8V
≤
V
CC
< 4.5V
I
OH
= -100µA
Min
Max
1
500
10
10
2
2
Units
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
-0.1
2
0
V
CC
x 0.7
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+1
0.4
2.4
0.2
V
CC
- 0.2
V
V
Doc. No. 1107, Rev. F
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C46R
PIN CAPACITANCE
Symbol
C
OUT(1)
C
IN(1)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0V
V
IN
= 0V
Max
5
5
Units
pF
pF
A.C. CHARACTERISTICS
(2)
V
CC
= 1.8V- 5.5V
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2
DC
Min
50
0
100
100
0.25
0.25
100
5
0.1
0.1
0.1
0.1
4
Max
V
CC
= 4.5V- 5.5V
Min
50
0
50
50
0.1
0.1
100
5
Max
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
MHz
POWER-UP TIMING
(1)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤
50ns
0.4V to 2.4V
4.5V
≤
V
CC
≤
5.5V
0.8V, 2.0V
4.5V
≤
V
CC
≤
5.5V
0.2V
CC
to 0.7V
CC
1.8V
≤
V
CC
≤
4.5V
0.5V
CC
1.8V
≤
V
CC
≤
4.5V
Current Source I
OLmax
/I
OHmax
; C
L
= 100pF
NOTE:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(2) Test conditions according to “A.C. Test Conditions” table.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1107, Rev. F
CAT93C46R
INSTRUCTION SET
Address
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
W RA L
Start Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
x8
A6-A0
A6-A0
A6-A0
11XXXXX
00XXXXX
10XXXXX
01XXXXX
Data
x8
x16
Comments
Read Address AN– A0
Clear Address AN– A0
D7-D0
D15-D0
Write Address AN– A0
Write Enable
Write Disable
Clear All Addresses
D7-D0
D15-D0
Write All Addresses
x16
A5-A0
A5-A0
A5-A0
11XXXX
00XXXX
10XXXX
01XXXX
DEVICE OPERATION
The CAT93C46R is a 1024-bit nonvolatile memory
intended for use with industry standard microproces-
sors. The CAT93C46R can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 9-bit instructions control the reading, writing and
erase operations of the device. When organized as X8,
seven 10-bit instructions control the reading, writing and
erase operations of the device. The CAT93C46R oper-
ates on a single power supply and will generate on chip
the high voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the rising edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin. The Ready/Busy
flag can be disabled only in Ready state; no change is
allowed in Busy state.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organization).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46R
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (t
PD0
or t
PD1
).
Sequential Read
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93C46R will automatically increment to the next
address and shift out the next data word. As long as CS
is continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
Read mode, only the initial data word is preceeded by a
dummy zero bit; all subsequent data words will follow
without a dummy zero bit.
Erase/Write Enable and Disable
The CAT93C46R powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C46R write
and erase instructions, and will prevent any accidental
writing or clearing of the device. Data can be read
normally from the device regardless of the write enable/
disable status.
Doc. No. 1107, Rev. F
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
