V
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
Product Features
PI74 SSTV16857 is designed for low-voltage operation,
V
DD
= V
DDQ
= 2.3V to 2.7V
Supports SSTL_2 Class I and II specifications
SSTL_2 Input and Output Levels
Designed for DDR Memory
Flow-Through Architecture
Package available:
48-pin 240 mil wide plastic TSSOP (A)
48-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductors PI74SSTV16857 series of logic circuits
are produced using the Companys advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTV16857 universal bus driver is designed
for 2.3V to 2.7V V
DD
operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
RESET must be supported with LVCMOS levels as V
REF
may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
Pericoms PI74SSTV16857 is characterized for operation from
0° to 70°C.
Logic Block Diagram
CLK
CLK
RESET
D1
38
39
34
48
35
R
D
CLK
1
Q1
V
REF
TO 13 OTHER CHANNELS
Product Pin Configuration
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK
CLK
VDD
GND
VREF
RESET
D8
D9
D10
D11
D12
VDD
GND
D13
D14
Product Pin Description
Pin Name
RESET
CLK
CLK
D
Q
GND
V
DD
V
DDQ
V
REF
Description
Reset (Active Low)
Clock Input
Clock Input
Data Input
Data Output
Ground
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
Inputs
RESET
L
H
Η
H
CLK
X
↑
↑
L or H
CLK
X
↓
↓
L or H
D
X
H
L
X
Outputs
Q
L
H
L
Q o
(2)
48-Pin
40
A, K
39
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Truth Table
(1)
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
Notes:
1. H = High Signal Level
2. Output level before the
L = Low Signal Level
indicated steady state
↑
= Transition LOW-to-HIGH
input conditions were
↓
= Transition HIGH-to-LOW
established.
X = Irrelevant
1
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06/04/01
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Ite m
Storage temperature
Supply voltage
Input voltage
(1)
O utput voltage
(1,2)
Input clamp current
O utput clamp current
Continuous output current
V
DD
, V
DDQ
or GND current/pin
Package Thermal Impedance
(3)
Symbol/Conditions
T
stg
V
DD
or V
DDQ
V
I
V
O
I
IK
, V
I
<0
I
OK
, V
O
<0
I
O
, V
O
= 0 to V
DDQ
I
DD
, I
DDQ
or I
GND
θJ
A
Ratings
65 to 150
0.5 to 3.6
0.5 to V
DD
+0.5
0.5 to V
DDQ
+0.5
50
±50
±50
±100
70
Units
°C
V
mA
°C/W
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Notes:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V
O
> V
DDQ
.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions
Parame te rs
V
DD
V
DDQ
V
REF
V
TT
V
IH
V
IL
V
IH
V
IL
V
IN
V
ID
V
IX
I
OH
I
OL
T
A
Supply Voltage
I/O Supply Voltage
Reference Voltage V
REF
= 0.5X V
DDQ
Termination Voltage
DC Input High Voltage
DC Input Low Voltage
Input High Voltage
Input Low Voltage
Input Voltage Level
Input Differential Voltage
RESET
Data Inputs
De s cription
M in.
2.3
2.3
1.15
V
REF
0.04
V
REF
+0.1
5
0.3
1.7
0.3
0.3
0.36
(V
DDQ
/2) 0.2
20
20
0
70
ºC
V
DDQ
+0.6
(V
DDQ
/2) +0.2
mA
Nom.
2.5
2.5
1.25
V
REF
M ax.
2.7
2.7
1.35
V
REF
+0.04
V
DDQ
+0.3
V
REF
0.15
V
DDQ
+0.3
0.8
V
Units
CLK,CLK
Cross Point Voltage of Differential Clock Pair
High- Level Output Current
Low- Level Output Current
Operating Free- Air Temperature
2
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06/04/01
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
DC Electrical Characteristics
Parame te rs
V
IK
V
OH
(Over the Operating Range, T
A
= 0°C to +70°C, V
DD
= 2.5V ±200mV, V
DDQ
= 2.5V ±200mV)
Te s t Conditions
I
I
= 18mA
I
OH
= 100µA
I
OH
= 16mA
I
OL
= 100µA
I
OH
=16mA
V
I
= V
DD
or GND
RESET = GND
V
I
= V
IH
(AC) or V
IL
(AC),
RESET = V
DD
RESET = V
DD,
V
I
= V
IH(AC)
or V
IL(AC)
,
CK and CK switching
50% duty cycle .
RESET = V
DD,
V
I
= V
IH(AC)
or V
IL(AC)
,
CK and CK switching 50%
duty cycle. One data input
switching at half clock
frequency, 50% duty cycle
V
I
= V
REF
±350mV
V
ICR
=1.25V, V
I(PP)
= 360mV
V
DD
2.3V
2.3V- 2.7V
2.3V
2.3V- 2.7V
2.3V
2.7V
M in.
Typ.
(4)
M ax.
1.2
Units
V
DD
0.2
1.95
0.2
0.35
5
100
TBD
mA
µA/
clock
MHz
µA
V
V
OL
I
I
I
DD
All Inputs
Standby (Static)
Operating (Static)
Dynamic operating
- clock only
I
DDD
Dynamic Operating
- per each data
input
TBD
I
O
= 0
2.7V
TBD
µA/
clock
MHz/
data
C
i
Data Inputs
CK and CK
2.5V
2.0
2.0
3.5
3.5
pF
Notes:
4. Typical values are at V
DD
= Nominal V
DD
, T
A
= +25°C.
3
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
Timing Requirements
(over recommended operating free-air temperature range
,
unless otherwise noted)
V
DD
= 2.5V ±0.2V
M in.
f
clock
t
PD
t
RST
t
SL
t
su
Clock frequency
Clock to output time
Reset to output time
Output slew rate
Setup time, fast slew rate
(5,7)
Setup time, slow slew rate
(6,7)
Hold time, fast slew rate
(5,7)
Hold time, slow slew rate
(6,7)
Data before CK
↑
, CK
↓
1
0.75
0.9
0.75
0.9
ns
TBD
M ax.
170
TBD
5
4
Units
MHz
ns
V/ns
t
h
Data after CK
↑
, CK
↓
Notes:
5. For data signal input slew rate
≥1V/ns.
6. For data signal input slew rate
≥0.5V/ns
and <1V/ns.
7. CLK, CLK signals input slew rates are
≥1V/ns.
(See test circuits and switching waveforms).
Switching characteristics
(over recommended operating free-air temperature range, unless otherwise noted.)
Parame te r
f
max
t
pd
t
phl
CLK , CLK
RESET
Q
Q
From
(Input)
To
(Output)
V
DD
= 2.5V ±0.2V
M in.
170
1.1
2.8
5.0
Typ.
M ax.
Units
MHz
ns
4
PS8460C
06/04/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
Test Circuit and Switching Waveforms
V
TT
LVCMOS
RESET
Input
I
DD(9)
V
DD
/2
V
DD
R
L
= 50
Ω
From Output
Under Test
TEST POINT
C
L
= 30pF
(8)
t
inact
10%
t
act
0V
90% I
DDH
I
DDL
Timing
Input
Load Circuit
Voltage and Current Waveforms
Input Active and Inactive Times
V
ICR
V
ICR
V
I(PP)
t
w
Input
V
REF
V
REF
V
IH
Output
t
PLH
V
TT
t
PHL
V
TT
V
OH
V
IL
V
OL
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Propagation Delay Times
Timing
Input
t
su
V
REF
LVCMOS
V
ICR
V
I(PP)
RESET
Input
V
IH
V
DD
/2
V
IL
t
PHL
V
OH
V
TT
V
OL
t
h
V
IH
V
REF
V
IL
Output
Input
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Parameter Measurement Information (V
DD
= 2.5V ±0.2V)
Notes:
8. C
L
includes probe and jig capacitance.
9. I
DD
tested with clock and data inputs held at V
DD
or GND, and I
O
= 0mA.
10. All input pulses are supplied by generators having the following characteristics:
PRR
≤10
MHz, Z
O
= 50Ω. Input slew rate = 1V/ns ±20% (unless otherwise specified).
11. The outputs are measured one at a time with one transition per measurement.
12. V
TT
= V
REF
= V
DDQ
/2
13. V
IH
= V
REF
+ 350mV (ac voltage levels) for SSTL inputs. V
IH
= V
DD
for LVCMOS input.
14. V
IL
= V
REF
+ 350mV (ac voltage levels) for SSTL inputs. V
IL
= GND for LVCMOS input.
15. t
PLH
and t
PHL
are the same as t
pd
.
5
PS8460C
06/04/01
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