ZL30123
SONET/SDH
Low Jitter Line Card Synchronizer
Data Sheet
May 2006
A full Design Manual is available to qualified customers.
To
register,
please
send
an
email
to
TimingandSync@Zarlink.com.
Ordering Information
ZL30123GGG
100 Pin CABGA
Trays
ZL30123GGG2 100 Pin CABGA*
Trays
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
•
DPLL2 provides a comprehensive set of features
for generating derived output clocks and other
general purpose clocks
Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
Provides 3 sync inputs for output frame pulse
alignment
Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
Configurable input to output delay, and output to
output phase alignment
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Supports IEEE 1149.1 JTAG Boundary Scan
Features
•
Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
Programmable output synthesizers (P0, P1)
generate clock frequencies from any multiple of
8 kHz up to 77.76 MHz in addition to 2 kHz
Provides two DPLLs which are independently
configurable through a serial peripheral interface
DPLL1 provides all the features necessary for
generating SONET/SDH compliant clocks including
automatic hitless reference switching, automatic
mode selection (locked, free-run, holdover), and
selectable loop bandwidth
•
•
•
•
•
•
•
•
•
•
trst_b tck tdi tms
tdo
dpll2_ref
dpll1_hs_en
dpll1_lock dpll1_holdover
diff0_en
diff1_en
osco
osci
Master
Clock
IEEE 1449.1
JTAG
ref
DPLL2
P0
Synthesizer
P1
Synthesizer
p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1
diff0
diff1
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
sync0
sync1
sync2
ref7:0
ref
DPLL1
sync2:0
Reference
Monitors
ref_&_sync_status
sync
fb_clk/fp
SONET/SDH
APLL
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
fb_clk
Feedback
Synthesizer
int_b
SPI Interface
Controller &
State Machine
sck
si
so
cs_b
rst_b
dpll1_mod_sel1:0
sdh_filter
filter_ref0
filter_ref1
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30123
Table of Contents
Data Sheet
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 DPLL Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3
Zarlink Semiconductor Inc.
ZL30123
List of Figures
Data Sheet
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Zarlink Semiconductor Inc.
ZL30123
List of Tables
Data Sheet
Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Zarlink Semiconductor Inc.
Embedded System
京公网安备 11010802033920号
EEWORLD
