ZL30406
SONET/SDH Clock Multiplier PLL
Data Sheet
Features
•
•
•
•
Meets jitter requirements of Telcordia GR-253-
CORE for OC-48, OC-12, and OC-3 rates
Meets jitter requirements of ITU-T G.813 for STM-
16, STM-4 and STM-1 rates
Provides four LVPECL differential output clocks at
77.76 MHz
Provides a CML differential clock programmable
to 19.44 MHz, 38.88 MHz, 77.76 MHz and
155.52 MHz
Provides a single-ended CMOS clock at
19.44 MHz
Provides enable/disable control of output clocks
Accepts a CMOS reference at 19.44 MHz
3.3 V supply
ZL30406QGC
ZL30406QGG1
March 2006
Ordering Information
64 Pin TQFP
Trays
64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
Description
The ZL30406 is an analog phase-locked loop (APLL)
designed to provide rate conversion and jitter
attenuation for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30406 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1
rates and ITU-T G.813 STM-16, STM-4 and STM-1
rates.
The ZL30406 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 77.76 MHz, a CML differential
clock programmable to 19.44 MHz, 38.88 MHz,
77.76 MHz and 155.52 MHz and a single-ended
CMOS clock at 19.44 MHz. The output clocks can
be individually enabled or disabled.
•
•
•
•
Applications
•
•
SONET/SDH line cards
Network Element timing cards
LPF
C77oEN-A
C77oEN-B
OC-CLKoEN
C77o
,
C155o
C19o, C38o,
CML-P/N outputs
OC-CLKoP/N
C19i
Frequency
& Phase
Detector
19.44MHz
C77oP/N-D
BIAS
Reference &
Bias circuit
Loop
Filter
Output
VCO
C77oP/N-A
C77oP/N-B
C77oP/N-C
Interface
Circuit
C19o
VDD GND
VCC
FS1-2
C19oEN
C77oEN-C
C77oEN-D
15
Figure 1 - Functional Block Diagram
1
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Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30406
Data Sheet
GND
VCC1
VCC
OC-CLKoN
OC-CLKoP
GND
VCC2
LPF
GND
GND
BIAS
OC-CLKoEN
C77oEN-A
C77oEN-B
C77oEN-C
C77oEN-D
GND
C77oN-A
C77oP-A
VCC
GND
C77oP-B
C77oN-B
VCC
GND
C77oN-C
C77oP-C
VCC
GND
C77oP-D
C77oN-D
VCC
64
2
62
60
58
56
54
52
50
48
46
44
65 - EP_GND
4
6
42
8
10
38
12
36
14
34
16
18
20
22
24
26
28
30
32
ZL30406
40
GND
VCC
VDD
GND
VCC
GND
VDD
GND
NC
GND
GND
NC
GND
C19o
VDD
GND
Figure 2 - TQFP 64 pin (Top View)
Change Summary
The following table captures the changes from the February 2005 issue.
Page
1
Item
Change
Updated Ordering Information.
Pin Description
Pin Description Table
Pin #
1
2
3
4
5
6
7
Name
GND
VCC1
VCC
OC-CLKoN
OC-CLKoP
GND
VCC2
Ground.
0 volt.
Positive Analog Power Supply.
+3.3 V ±10%
Positive Analog Power Supply.
+3.3 V ±10%
SONET/SDH Clock (CML Output).
These outputs provide a programmable
differential CML clock at 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz.
The output frequency is selected with FS2 and FS1 pins.
Ground.
0 volt
Positive Analog Power Supply.
+3.3 V ±10%
Description
GND
VDD
NC
NC
NC
VDD
IC
FS2
FS1
C19oEN
GND
C19i
VDD
GND
NC
GND
2
Zarlink Semiconductor Inc.
ZL30406
Pin Description Table (continued)
Pin #
8
9
10
11
12
Name
LPF
GND
GND
BIAS
OC-CLKoEN
Description
Data Sheet
Low Pass Filter (Analog). Connect to this pin external RC network (R
F
and C
F
)
for the low pass filter.
Ground.
0 volt
Ground.
0 volt
Bias.
See Figure 11 for the recommended bias circuit.
SONET/SDH Clock Enable (CMOS Input).
If tied high this control pin enables
the OC-CLKoP/N differential driver. Pulling this input low disables the output
clock without deactivating differential drivers.
C77 Clock Output Enable A (CMOS Input).
If tied high this control pin
enables the C77oP/N-A output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
C77 Clock Output Enable B (CMOS Input).
If tied high this control pin
enables the C77oP/N-B output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
C77 Clock Output Enable C (CMOS Input).
If tied high this control pin
enables the C77oP/N-C output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
C77 Clock Output Enable D (CMOS Input).
If tied high this control pin
enables the C77oP/N-D output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
Ground.
0 volt
Positive Digital Power Supply.
+3.3 V ±10%
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Positive Digital Power Supply.
+3.3 V ±10%
Internal Connection.
Connect this pin to Ground (GND).
Frequency Select 2-1 (CMOS Input).
These inputs program the clock
frequency on the OC-CLKo output. The possible output frequencies are
19.44 MHz (00), 38.88 MHz (01), 77.76 MHz (10), 155.52 MHz (11).
C19o Output Enable (CMOS Input).
If tied high this control pin enables the
C19o output clock. Pulling this pin low forces output driver into a high
impedance state.
Ground.
0 volt
C19 Reference Input (CMOS Input).
This pin is a single-ended input reference
source used for synchronization. This pin accepts 19.44 MHz.
Positive Digital Power Supply.
+3.3 V ±10%
Ground.
0 volt
No internal bonding Connection. Leave unconnected.
Ground.
0 volt.
C77oEN-A
13
C77oEN-B
14
C77oEN-C
15
C77oEN-D
16
17
18
19
20
21
22
23
24
25
26
GND
VDD
NC
NC
NC
VDD
IC
FS2
FS1
C19oEN
27
28
29
30
31
32
GND
C19i
VDD
GND
NC
GND
3
Zarlink Semiconductor Inc.
ZL30406
Pin Description Table (continued)
Pin #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Name
GND
VDD
C19o
GND
NC
GND
GND
NC
GND
VDD
GND
VCC
GND
VDD
VCC
GND
VCC
C77oN-D
C77oP-D
GND
VCC
C77oP-C
C77oN-C
GND
VCC
C77oN-B
C77oP-B
GND
VCC
C77oP-A
C77oN-A
GND
EP_GND
Ground.
0 volt
Positive Digital Power Supply.
+3.3 V ±10%
Description
Data Sheet
C19 Clock Output (CMOS Output).
This pin provides a single-ended CMOS
clock at 19.44 MHz.
Ground.
0 volt
No internal bonding Connection. Leave unconnected.
Ground.
0 volt
Ground.
0 volt
No internal bonding Connection. Leave unconnected.
Ground.
0 volt
Positive Digital Power Supply.
+3.3 V ±10%
Ground.
0 volt
Positive Analog Power Supply.
+3.3 V ±10%
Ground.
0 volt
Positive Digital Power Supply.
+3.3 V ±10%
Positive Analog Power Supply.
+3.3 V ±10%
Ground.
0 volt
Positive Analog Power Supply.
+3.3 V ±10%.
C77 Clock Output (LVPECL Output).
These outputs provide a differential
LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated
to decrease supply current.
Ground.
0 volt
Positive Analog Power Supply.
+3.3 V ±10%.
C77 Clock Output (LVPECL Output).
These outputs provide a differential
LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated
to decrease supply current.
Ground.
0 volt
Positive Analog Power Supply.
+3.3 V ±10%.
C77 Clock Output (LVPECL Output).
These outputs provide a differential
LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated
to decrease supply current.
Ground.
0 volt
Positive Analog Power Supply.
+3.3 V ±10%.
C77 Clock Output (LVPECL Output).
These outputs provide a differential
LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated
to decrease supply current.
Ground.
0 volt
Exposed die Pad Ground.
0 volt (connect to GND)
4
Zarlink Semiconductor Inc.
ZL30406
1.0
Functional Description
Data Sheet
The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for
SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the
ZL30406 is shown in Figure 1 and a brief description is presented in the following sections.
1.1
Frequency/Phase Detector
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback
signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase
difference between the two. This error signal is passed to the Loop Filter circuit and averaged to control the
VCO frequency.
1.2
Loop Filter
The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an
input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external
capacitor and resistor connected to the LPF pin and ground as shown below.
ZL30406
LPF
Internal Loop
Filter
R
F
C
F
RF=8.2 kΩ, CF=470 nF
(for 14 kHz PLL bandwidth)
Figure 3 - External Loop Filter
1.3
VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the
voltage of the error signal, generates a primary frequency. The VCO output is connected to the Output Interface
Circuit that divides VCO frequency and buffers generated clocks.
5
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