STV160NF02LA
N-CHANNEL 20V - 0.0018Ω - 160A PowerSO-10
STripFET™ POWER MOSFET
TYPE
STV160NF02LA
s
s
s
s
s
s
s
V
DSS
20 V
R
DS(on)
< 0.0027
Ω
I
D
160 A
TYPICAL R
DS
(on) = 0.0018
Ω
LOW THRESHOLD DRIVE
ULTRA LOW ON-RESISTANCE
ULTRA FAST SWITCHING
100% AVALANCHE TESTED
VERY LOW GATE CHARGE
LOW PROFILE, VERY LOW PARASITIC
INDUCTANCE PowerSO-10 PACKAGE
10
1
PowerSO-10
INTERNAL SCHEMATIC DIAGRAM
DESCRIPTION
The
STV160NF02LA
represents the second gen-
eration of Application Specific STMicroelectronics
well established STripFET™ process based on a
very unique strip layout design. The resulting
MOSFET shows unrivalled high packing density
with ultra low on-resistance and superior switching
charactestics. Process simplification also trans-
lates into improved manufacturing reproducibility.
This device is particularly suitable for high current,
low voltage switching application where efficiency
is crucial
APPLICATIONS
s
BUCK CONVERTERS IN HIGH
PERFORMANCE TELECOM AND VRMs DC-
DC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
(**)
I
D
I
DM
(
q
)
P
TOT
E
AS
(1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 kΩ)
Gate- source Voltage
Drain Current (continuos) at T
C
= 25°C
Drain Current (continuos) at T
C
= 100°C
Drain Current (pulsed)
Total Dissipation at T
C
= 25°C
Derating Factor
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
CONNECTION DIAGRAM (TOP VIEW)
Value
20
20
± 15
160
113
640
210
1.4
330
–65 to 175
175
Unit
V
V
V
A
A
A
W
W/°C
mJ
°C
°C
(
q
) Pulse width limited by safe operating area
Note: Marking will be STV160NF02AL
December 2000
(1) V
DD
= 35V, I
D
= 45A, R
G
= 22Ω
,
L = 330µH, Starting T
j
=25°C
(**)Limited only maximum junction temperature allowed by
PowerSO-10
1/8
STV160NF02LA
THERMAL DATA
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose
0.71
50
300
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS
(TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol
V
(BR)DSS
I
DSS
I
GSS
Parameter
Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Test Conditions
I
D
= 250 µA, V
GS
= 0
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 °C
V
GS
= ± 15 V
Min.
20
1
10
±100
Typ.
Max.
Unit
V
µA
µA
nA
ON (1)
Symbol
V
GS(th)
R
DS(on)
Parameter
Gate Threshold Voltage
Static Drain-source On
Resistance
Test Conditions
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10 V, I
D
= 80 A
V
GS
= 10 V, I
D
= 45 A
V
GS
= 8 V, I
D
= 80 A
V
GS
= 5 V, I
D
= 40 A
V
GS
= 10 V, I
D
=80 A;T
j
= 175 °C
V
GS
= 8 V, I
D
=80 A; T
j
= 175 °C
V
GS
= 5 V, I
D
=40 A; T
j
= 125 °C
V
DS
> I
D(on)
x R
DS(on)max,
V
GS
= 10V
160
Min.
1
1.8
1.76
1.9
3.8
2.7
2.7
3.7
6.4
6
8
14
Typ.
Max.
Unit
V
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
A
I
D(on)
On State Drain Current
DYNAMIC
Symbol
g
fs
(1)
R
g
C
iss
C
oss
C
rss
C
iss
C
oss
C
rss
L
S
Parameter
Forward Transconductance
Gate resistance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Internal Source Inductance
Test Conditions
V
DS
> I
D(on)
x R
DS(on)max,
I
D
= 80A
V
DS
= 0 V, f = 1 MHz, V
GS
= 0
V
DS
= 15 V, f = 1 MHz, V
GS
= 0
Min.
Typ.
210
1.1
5500
3210
750
8400
14500
5800
3
Max.
Unit
S
Ω
pF
pF
pF
pF
pF
pF
nH
V
DS
= 0 V, f = 1 MHz, V
GS
= 0
From the Lead End (6mm from
Package Body) to the Die
Center
L
D
Internal Drain Inductance
Not Available on Surface Mounting
Package
2/8
STV160NF02LA
ELECTRICAL CHARACTERISTICS
(CONTINUED)
SWITCHING ON
Symbol
t
d(on)
t
r
Q
g
Q
gs
Q
gd
Parameter
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
V
DD
= 15 V, I
D
= 80 A
R
G
= 4.7Ω V
GS
= 10V
(see test circuit, Figure 3)
V
DD
= 16 V, I
D
= 160 A,
V
GS
= 10 V
Min.
Typ.
30
650
130
20
54
175
Max.
Unit
ns
ns
nC
nC
nC
SWITCHING OFF
Symbol
t
d(off)
t
f
t
d(off)
t
r(Voff)
t
f
t
c
Parameter
Turn-off-Delay Time
Fall Time
Turn-off Delay Time
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
V
DD
= 15 V, I
D
= 80 A,
R
G
= 4.7Ω, V
GS
= 10 V
(see test circuit, Figure 5)
Vclamp = 16 V, I
D
= 40 A
R
G
= 4.7Ω, V
GS
= 10V
Min.
Typ.
105
200
90
45
125
180
Max.
Unit
ns
ns
ns
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t
rr
Q
rr
I
RRM
Parameter
Source-drain Current
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 160 A, V
GS
= 0
I
SD
= 160A, di/dt = 100A/µs,
V
DD
= 15V, T
j
= 25°C
(see test circuit, Figure 5)
90
225
5
Test Conditions
Min.
Typ.
Max.
160
640
1.5
Unit
A
A
V
ns
nC
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
3/8
STV160NF02LA
Output Characteristics
Tranfer Characteristics
Tranconductance
Static Drain-Source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STV160NF02LA
Normalized Gate Thereshold Voltage vs Temp.
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
Basic Schematic For Motherboard VRM Whith
Synchronous Rectification
Basic Schematic Mosfets Switch Used In
Secondary Side Of a Froward Convert
5/8
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