ZL50017QCC datasheet, PDF - EEWORLD Datasheet

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ZL50017QCC: Description1 K Digital Switch; CategoryWireless rf/communication Telecom circuit; File Size473KB，51 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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ZL50017QCC Overview

1 K Digital Switch

ZL50017QCC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Zarlink Semiconductor (Microsemi)
package instruction	LFQFP, QFP256,1.2SQ,16
Reach Compliance Code	compliant
JESD-30 code	S-PQFP-G256
JESD-609 code	e0
length	28 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	256
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP256,1.2SQ,16
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	225
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	DIGITAL TIME SWITCH
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	28 mm

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ZL50017

1 K Digital Switch

Data Sheet

Features

•

1024 channel x 1024 channel non-blocking digital

Time Division Multiplex (TDM) switch at 4.096,

8.192 or 16.384 Mbps

16 serial TDM input, 16 serial TDM output

streams

Output streams can be configured as bi-

directional for connection to backplanes

Exceptional input clock cycle to cycle variation

tolerance (20 ns for all rates)

Per-stream input bit delay with flexible sampling

point selection

Per-stream output bit and fractional bit

advancement

Per-channel constant or variable throughput

delay for frame integrity and low latency

applications

Per-channel high impedance output control

Per-channel message mode

Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz

Input frame pulses:61 ns, 122 ns, 244 ns

Control interface compatible with Intel and

Motorola 16-bit non-multiplexed buses

Connection memory block programming

•

Ordering Information

ZL50017GAC

ZL50017QCC

ZL50017QCG1

ZL50017GAG2

256 Ball PBGA

256 Lead LQFP

256 Lead LQFP*

256 Ball PBGA**

Trays

Trays, Bake &

Drypack

Trays, Bake &

Drypack

November 2006

*Pb Free Matte Tin

**Pb Free Tin/Silver/Copper

-40°C to +85°C

Supports ST-BUS and GCI-Bus standards for

input and output timing

IEEE-1149.1 (JTAG) test port

3.3 V I/O with 5 V tolerant inputs; 1.8 V core

voltage

Applications

•

PBX and IP-PBX

Small and medium digital switching platforms

Remote access servers and concentrators

Wireless base stations and controllers

Multi service access platforms

Digital Loop Carriers

Computer Telephony Integration

RESET

ODE

DD_CORE

DD_IO

DD_COREA

DD_IOA

STi[15:0]

FPi

CKi

MODE_4M0

MODE_4M1

S/P Converter

Data Memory

P/S Converter

STio[15:0]

TMS

Test Port

Input Timing

Connection Memory

TDi

TDo

TCK

TRST

Internal Registers &Microprocessor Interface

DS_RD

R/W_WR

A[13:0]

Figure 1 - ZL50017 Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MOT_INTEL

DTA_RDY

D[15:0]

ZL50017

Data Sheet

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.0 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 BGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 QFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.0 Data Rates and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Input Clock (CKi) and Input Frame Pulse (FPi) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 ST-BUS and GCI-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2 Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.3 Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.4 Fractional Output Bit Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.0 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10.2 Device Initialization on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

12.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

13.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

14.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

14.1 Memory Address Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

14.2 Connection Memory Low (CM_L) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

15.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

16.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Zarlink Semiconductor Inc.

ZL50017

Data Sheet

List of Figures

Figure 1 - ZL50017 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2 - ZL50017 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) . . . . . . . . . . . . . . . . . . . 7

Figure 3 - ZL50017 256-Lead 28 mm x 28 mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7 - Input Bit Delay Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9 - Input Bit Delay and Factional Sampling Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10 - Output Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11 - Output Fractional Bit Advancement Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 15 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 16 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 17 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 18 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 19 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 20 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 21 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 22 - ST-BUS Input and Output Timing Diagram when Operated at 2, 4, 8 and 16 Mbps . . . . . . . . . . . . . . 47

Figure 23 - GCI-Bus Input and Output Timing Diagram when Operated at 2, 4, 8 and 16 Mbps . . . . . . . . . . . . . 48

Zarlink Semiconductor Inc.

ZL50017QCC Related Products

	ZL50017QCC	ZL50017GAC	ZL50017_0611	ZL50017QCG1	ZL50017GAG2
Description	1 K Digital Switch	1 K Digital Switch	1 K Digital Switch	1 K Digital Switch	1 K Digital Switch
Maker	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	-	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)
package instruction	LFQFP, QFP256,1.2SQ,16	BGA, BGA256,16X16,40	-	LFQFP,	BGA,
Reach Compliance Code	compliant	compliant	-	unknown	unknown
JESD-30 code	S-PQFP-G256	S-PBGA-B256	-	S-PQFP-G256	S-PBGA-B256
JESD-609 code	e0	e0	-	e3	e1
length	28 mm	17 mm	-	28 mm	17 mm
Number of functions	1	1	-	1	1
Number of terminals	256	256	-	256	256
Maximum operating temperature	85 °C	85 °C	-	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	BGA	-	LFQFP	BGA
Package shape	SQUARE	SQUARE	-	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY	-	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.8 mm	-	1.6 mm	1.8 mm
Nominal supply voltage	1.8 V	1.8 V	-	1.8 V	1.8 V
surface mount	YES	YES	-	YES	YES
Telecom integrated circuit types	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH	-	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH
Temperature level	INDUSTRIAL	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	MATTE TIN	TIN SILVER COPPER
Terminal form	GULL WING	BALL	-	GULL WING	BALL
Terminal pitch	0.4 mm	1 mm	-	0.4 mm	1 mm
Terminal location	QUAD	BOTTOM	-	QUAD	BOTTOM
width	28 mm	17 mm	-	28 mm	17 mm

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