PDSP16318 MC
PDSP16318 MC
Complex Accumulator
DS3761
ISSUE 2.1
November 1998
The PDSP16318 contains two independent 20-bit Adder/
Subtractors combined with accumulator registers and shift
structures. The four port architecture permits full 10MHz
throughout in FFT and filter applications.
Two PDSP16318s combined with a single PDSP16112A
Complex Multiplier provide a complete arithmetic solution for
a Radix 2 DIT FFT Butterfly. A new complex Butterfly result
can be generated every 100ns allowing 1k complex FTT's to
to be executed in 512µs.
GC100
FEATURES
s
s
s
s
s
s
s
s
s
s
Full 10MHz Throughout in FFT Applications
Four Independent 16-bit I/O Ports
20-bit Addition or Accumulation
Fully Compatible with PDSP16112 Complex Multiplier
On Chip Shift Structures for Result Scaling
Overflow Detection
Independent Three-State Outputs and Clock
Enables for 2 Port 10MHz Operation
1.4 micron CMOS
500mW Maximum Power Dissipation
100 pin ceramic QFP
Fig.1 Pin connections
Rev
Date
NOTE
A
B
C
D
MAR 1993 NOV 1998
Polyimide is used as an inter-layer dielectric and as
glassivation.
ORDERING INFORMATION
PDSP16318/MC/GC1R (Ceramic QFP Package -
MIL STD 883 Screening)
A
REG
DELAY
B
SHIFT
A
REG
C
A
SHIFT
B
REG
B
REG
D
Fig.2 PDSP16318 simplified block diagram
1
PDSP16318 MC
CEA
DEL
ASR
S2:0
OEC
16
A
A REG
16
8
CYCLE
DELAY
MUX
20
B
20
SHIFT
A
16
REG
16
D
20
MUX
REG
20
CLK
20
MS
MUX
20
REG
CLR
OVR
A
16
SHIFT
16
B
REG
16
B
20
REG
16
D
REG
ASI
OED
Fig.2 Block diagram
FUNCTIONAL DESCRIPTION
The PDSP16318 is a Dual 20-bit Adder/Subtractor
configured to supprt Complex Arithmetic. The device may be
used with each of the adders allocated to real or imaginary
data (e.g. Complex Conjugation), the entire device allocated
to Real or Imaginary Data (e.g. Radix 2 Butterflys) or each of
the adders configured as accumulators and allocated to real
or imaginary data (Complex Filters). Each of these modes
ensures that a full 10MHz throughput is maintained through
both adders, the first and last mode illustrating true Complex
operation, where both real and imaginary data is handled by
the single device.
Both Adder/Subtractors may be controlled
independently via the ASR and ASI inputs. These controls
permit A + B, A - B, B - A or pass A operations, where the A
input to the Adder is derived from the input multiplexer. The
CLR control line allows the clearing of both accumaltor
registsers. The two multiplexers may be controlled via the MS
inputs, to select either new input data, or fed-back data from
the accumulator registers. The PDSP16318 contains an 8-
cycle deskew register selected via the DEL control. This
deskew register is used in the FFT applications to ensure
correct phasing of data that has not passed through the
PDSP16112 Complex Multiplier.
The 16-bit outputs from the PDSP16318 are derived from
the 20-bit result generated by the Adders. The three bit S2:0
input selects eight different shifted output formats ranging
from the most significant 16 bits of the 20-bit data, to the least
significant 13 bits of the 20-bit data. In this mode the 14th, 15th
and 16th bits of the output are set to zero. The shift selected
is applied to both adder outputs, and determines the function
of the OVR flag. The OVR flag becomes active when either of
the two adders produces a result that has more significant
digits than the MSB of the 16-bit output from the device. In this
manner all cases when invalid data appears on the output are
flagged.
2
PDSP16318 MC
Symbol
A15:0
B15:0
C15:0
D15:0
CLK
CEA
CEB
OEC
OED
OVR
Type
Input
Input
Output
Output
Input
Input
Input
Input
Input
Output
Description
Data
presented to this input is loaded into the input register on the rising edge of CLK. A15 is the MSB.
Data
presented to this input is loaded into the input register on the rising edge of CLK. B15 is the MSB
and has the same weighting as A15.
New
data
appears on this output after the rising edge of CLK. C15 is the MSB.
New
data
appears on this output after the rising edge of CLK. D15 is the MSB.
Common Clock
to all internal registers
Clock enable:
when low the clock to the A input register is enabled.
Clock enable:
when low the clock to the B input register is enabled.
Output enable:
Asynchronous 3-state output control: The C outputs are in a high impedance
state when this input is high.
Output enable:
Asynchronous 3-state output control: The D outputs are in a high impedance
state when this input is high.
Overflow flag:
This flag will go high in any cycle during which either the output data overflows the number
range selected or either of the adder results overflow. A new OVR appears after the rising edge of the
CLK.
Add/subtract Real:
Control input for the 'Real' adder. This input is latched by the rising edge of clock.
Add/subtract Imag:
Control input for the 'Imag' adder. This input is latched by the rising edge of clock.
Accumulator Clear:
Common accumulator clear for both Adder/Subtractor units. This input is latched by
the rising edge of CLK.
Mux select:
Control input for both adder multiplexers. This input is latched by the rising edge of CLK.
When high the feedback path is selected.
Scaling control:
This input selects the 16-bit field from the 20-bit adder result that is routed to the outputs.
This input is latched by the rising edge of CLK.
Delay Control:
This input selects the delayed input to the real adder for operations involving the
PDSP16112. This input is latched by the rising edge of CLK.
+5V supply:
Both Vcc pins must be connected.
0V supply:
Both GND pins must be connected.
ASR1:0
ASI1:0
CLR
MS
S2:0
DEL
VCC
GND
Input
Input
Input
Input
Input
Input
Power
Ground
GG pin Function GG pin
77
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
5
D7
D8
D9
D10
GND
VCC
D11
D12
D13
D14
D15
C15
C14
C13
C12
VCC
GND
C11
C10
C9
C8
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Function GG pin Function GG pin Function
C7
C6
C5
C4
C3
C2
C1
C0
OED
OEC
S2
S1
S0
MS
ASI1
ASI0
DEL
CLR
ASR1
ASR0
A0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
CEA
B15
B14
B13
B12
B11
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
CLK
CEB
OVR
D0
D1
D2
D3
D4
D5
D6
Device Pinout for ceramic QFP (GC100)
3
PDSP16318 MC
ASR or ASI
ASX1 ASX0
0
0
1
1
0
1
0
1
ALU Function
A+B
A
A-B
B-A
DEL
0
1
Delay Mux Control
A port input
Delayed A port input
MS
0
1
Real and Imag' Mux Control
B port input/Del mux output
C accumulator/D accumualtor
S2:0
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
19
15
18
14
15
17
13
14
15
16
12
13
14
15
15
11
12
13
14
15
14
10
11
12
13
14
15
13
9
10
11
12
13
14
15
12
8
9
10
11
12
13
14
15
11
7
8
9
10
11
12
13
14
Adder result
10
6
7
8
9
10
11
12
13
9
5
6
7
8
9
10
11
12
8
4
5
6
7
8
9
10
11
7
3
4
5
6
7
8
9
10
6
2
3
4
5
6
7
8
9
5
1
2
3
4
5
6
7
8
4
0
1
2
3
4
5
6
7
3
2
1
0
0
1
2
3
4
5
6
0
1
2
3
4
5
0
1
2
3
4
0
1
2
3
NOTE
This table shows the portion of the adder result passed to the D15:0 and C15:0 outputs. Where fewer than 16 adder bits are selected
the output data is padded with zeros.
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply voltage V
CC
-0.5V to 7.0V
-0.9V to V
CC
+0.9V
Input voltage V
IN
Output voltage V
OUT
-0.9V to V
CC
+0.9V
Clamp diode current per I
k
(see Note 2)
18mA
Static discharge voltage (HMB) V
STAT
500V
-65°C to +150°C
Storage temperature range T
S
Ambient temperature with
power applied T
amb
Military
-55°C to +125°C
Junction temperature
150°C
1000mW
Package power dissipation P
TOT
THERMAL CHARACTERISTICS
Package Type
GC
θ
JC
°
C/W
12
NOTES
1. Excedding these ratings may cause permanent damage.
Functional operation under these conditions is not implied.
2. Maximum dissipation or 1 second should not be exceedeed, only
one output to be tested at any one time.
3. Exposure to absolute maximum ratings for extended periods may
affect device reliability.
4
PDSP16318 MC
Test
Waveform - measurement level
Delay from ouput
high to output
high impedance
VH
0.5V
Delay from ouput
low to output
high impedance
VL
0.5V
Delay from ouput
high impedance to
Output low
1.5V
0.5V
Delay from ouput
high impedance to
Output high
1.5V
0.5V
NOTES
1. VH - Voltage reached when output driven high
2. VL - Voltage reached when output driven low
I
OL
DUT
1.5V
100p
I
OH
5
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