PDSP16515A datasheet, PDF - EEWORLD Datasheet

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PDSP16515A: DescriptionStand Alone FFT Processor; File Size175KB，25 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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PDSP16515A Overview

Stand Alone FFT Processor

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PDSP16515A

Stand Alone FFT Processor

Advance Information

DS3922

ISSUE 2.0

April 1999

Features

Ordering Information

Completely self contained FFT Processor

Pin and functionally compatible with the

PDSP16510A

Expanded width internal RAM supports up to 1024

complex points

18 bit internal data bus with block floating point

arithmetic for increased dynamic range

500 MIP operation gives 87 microsecond

transformation times for 1024 points

Up to 45MHz sampling rates with multiple devices.

Up to 85dB noise rejection

A choice of internal window operators with no

external ROM provide up to 67dB side lobe

attenuation.

84 pin PGA or 132 pin surface mount package

Associated Products

PDSP16330

PDSP16256

PDSP16350

PDSP16510A

Pythagoras Processor.

Programmable FIR Filter.

I/Q Splitter / NCO

Stand Alone FFT Processor

( Commercial - PGA

Package )

PDSP16515A C0 GC

( Commercial - Leaded

Chip Carrier )

PDSP16515A B0 AC

( Industrial - PGA

Package )

PDSP16515A B0 GC

( Industrial -

Leaded

Chip Carrier )

PDSP16515A A0 AC

( Military - PGA

Package )

PDSP16515A A0 GC

( Military - Leaded Chip

Carrier )

PDSP16515A/MA/GCPR

( Military - Screened

Leaded Chip Carrier. See separate datasheet for

details )

PDSP16515A C0 AC

The PDSP16515A performs Forward or Inverse Fast

Fourier Transforms on complex or real data sets

containing up to 1024 points. Data and coefficient input

are both represented by 16 bits. Data is expanded

internally to 18 bits and subject to Block Floating Point

arithmetic to preserve a greater dynamic range.

An internal RAM is provided which can hold up to 1024

complex data points. This removes the memory transfer

bottleneck, inherent in building block solutions. Its

organisation allows the PDSP16515A to

simultaneously input new data, transform data stored in

the RAM, and to output previous results. No external

buffering is needed for transforms containing up to 256

points, and the PDSP16515A can be directly connected

to an A/D converter to perform continuous transforms.

The user can choose to overlap data blocks by either

0%, 50%, or 75%. Inputs and outputs are synchronous

to the 45MHz system clock used for internal operations.

A 1024 point complex transform can be completed in

some 87µs, which is equivalent to throughput rates of

500 million operations per second. Multiple devices can

be connected in parallel in order to increase the

sampling rate up to the 45MHz system clock. Six

devices are needed to give the maximum performance

with 1024 point transforms.

Either a Hamming or a Blackman-Harris window

operator can be internally applied to the incoming real or

complex data. The latter gives 67dB side lobe

attenuation. The operator values are calculated

internally and do not require an external ROM nor do

they incur any time penalty.

The increased internal bus size together with block

floating arithmetic produce up to 85dB of noise

rejection.

The device outputs the real and imaginary components

of the frequency bins. These can be directly connected

to the PDSP16330 in order to produce magnitude and

phase values from the complex data.

PDSP16515A

SIGNAL

D15:0

AUX15:0

TYPE

DESCRIPTION

Data input during real only mode. The real component in complex data mode.

When DEF is active AUX15:0 are used to define the operating mode as defined in Table 3.

When DEF is in-active AUX15:0 either provide the 16 bit imaginary component of complex

input data, or a second set of real only inputs.

These pins output the real component of the transformed data when DAV and DEN are active.

Otherwise they are high impedance.

These pins output the imaginary component of the transformed data when DAV and DEN are

active. Otherwise they are high impedance.

The high going edge of DEF is used to internally latch the contents of AUX15:0, which then

define the operating mode. In the simplest system DEF is a power on reset. When DEF is low

the internal control logic is reset.

System clock used for internal computations.

These pins indicate the number of shifts towards the binary point which have occurred as the

result of the conditional scaling logic. When the data path right shift is restricted to 2 places

per pass, state 15 is used to indicate an overflow and only a total of 14 shifts is possible.

This flag indicates that data is being loaded into the device. It goes active in response to an

INEN input, and may be programmed to go in-active after the complete, one quarter, or one

half a data block has been loaded.

The use of this input is mode dependent. It is either used as an active low, load enabling,

signal for the DIS strobe, or it is used to initiate a new block load operation.

The rising edge of this input is used to load data into the device.

The rising edge of this input is used to dump data from the device. In most applications it may

be tied to the DIS input, even if the output rate must be higher than the input rate because of

overlapped data blocks. The DIS input is then internally divided down.

An active low signal that indicates that a transform is complete. Transformed data will then

be output in normal sequential order using DOS. It may be optionally programmed to be

delayed by 24 DOS strobes to match the delay through a PDSP16330.

This input is used to enable the data dump operation when DAV has gone active. If it is tied

low the device will automatically dump data when DAV goes active. Otherwise the device will

wait for the enabling signal to go low before the dump operation commences.

Only available in the 132 pin GC package. When high the block floating logic is disabled.

+5V pins

Ground pins

R15:0

I15:0

DEF

SCLK

S3:0

LFLG

INEN

DIS

DOS

DAV

DEN

DISAB

VDD

GND

NOTE.

All references to DEF, INEN, DAV, and DEN within the text do not contain the bar designator, signifying an active

low signal. This is considered to be implied by the signal name and is not meant to imply a change in the signal

function.

Functional Operation

The PDSP16515A performs decimation in time, radix 4,

forward or inverse Fast Fourier Transforms. Data is loaded

into an internal workspace RAM in normal sequential order,

processed, and then dumped in the correct order. With real

only input data the processing time can approximately be halved

for a given transform size. Two real inputs then replace a single

complex input, and are processed in parallel.

Either a Blackman-Harris or a Hamming window can be

PDSP16515A Related Products

	PDSP16515A	PDSP16515AB0AC	PDSP16515AC0AC	PDSP16515AC0GC	PDSP16515AMA	PDSP16515AGCPR	PDSP16515AA0GC	PDSP16515AB0GC	PDSP16515AA0AC	PDSP16510A
Description	Stand Alone FFT Processor	Stand Alone FFT Processor	Stand Alone FFT Processor	Stand Alone FFT Processor	Stand Alone FFT Processor	Stand Alone FFT Processor	Stand Alone FFT Processor	Stand Alone FFT Processor	Stand Alone FFT Processor	Stand Alone FFT Processor
Is it Rohs certified?	-	incompatible	incompatible	incompatible	-	-	incompatible	incompatible	incompatible	-
package instruction	-	PGA, PGA84,13X13MOD	PGA, PGA84,13X13MOD	QFF, QFL132,.95SQ,25	-	-	QFF, QFL132,.95SQ,25	QFF, QFL132,.95SQ,25	PGA, PGA84,13X13MOD	-
Reach Compliance Code	-	compli	compli	compli	-	-	compli	compli	compli	-
ECCN code	-	3A001.A.3	3A001.A.3	3A001.A.3	-	-	3A001.A.2.C	3A001.A.3	3A001.A.2.C	-
boundary scan	-	NO	NO	NO	-	-	NO	NO	NO	-
maximum clock frequency	-	45 MHz	45 MHz	45 MHz	-	-	40 MHz	45 MHz	40 MHz	-
External data bus width	-	16	16	16	-	-	16	16	16	-
JESD-30 code	-	S-CPGA-P84	S-CPGA-P84	S-CQFP-F132	-	-	S-CQFP-F132	S-CQFP-F132	S-CPGA-P84	-
JESD-609 code	-	e0	e0	e0	-	-	e0	e0	e0	-
length	-	33.528 mm	33.528 mm	24.1935 mm	-	-	24.1935 mm	24.1935 mm	33.528 mm	-
low power mode	-	NO	NO	NO	-	-	NO	NO	NO	-
Number of terminals	-	84	84	132	-	-	132	132	84	-
Maximum operating temperature	-	85 °C	70 °C	70 °C	-	-	125 °C	85 °C	125 °C	-
Output data bus width	-	16	16	16	-	-	16	16	16	-
Package body material	-	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	-	-	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	-
encapsulated code	-	PGA	PGA	QFF	-	-	QFF	QFF	PGA	-
Encapsulate equivalent code	-	PGA84,13X13MOD	PGA84,13X13MOD	QFL132,.95SQ,25	-	-	QFL132,.95SQ,25	QFL132,.95SQ,25	PGA84,13X13MOD	-
Package shape	-	SQUARE	SQUARE	SQUARE	-	-	SQUARE	SQUARE	SQUARE	-
Package form	-	GRID ARRAY	GRID ARRAY	FLATPACK	-	-	FLATPACK	FLATPACK	GRID ARRAY	-
Peak Reflow Temperature (Celsius)	-	225	225	225	-	-	225	225	225	-
power supply	-	5 V	5 V	5 V	-	-	5 V	5 V	5 V	-
Certification status	-	Not Qualified	Not Qualified	Not Qualified	-	-	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	-	6.15 mm	6.15 mm	2.49 mm	-	-	2.49 mm	2.49 mm	6.15 mm	-
Maximum supply voltage	-	5.5 V	5.25 V	5.25 V	-	-	5.5 V	5.5 V	5.5 V	-
Minimum supply voltage	-	4.5 V	4.75 V	4.75 V	-	-	4.5 V	4.5 V	4.5 V	-
Nominal supply voltage	-	5 V	5 V	5 V	-	-	5 V	5 V	5 V	-
surface mount	-	NO	NO	YES	-	-	YES	YES	NO	-
technology	-	CMOS	CMOS	CMOS	-	-	CMOS	CMOS	CMOS	-
Temperature level	-	INDUSTRIAL	COMMERCIAL	COMMERCIAL	-	-	MILITARY	INDUSTRIAL	MILITARY	-
Terminal surface	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	-	PIN/PEG	PIN/PEG	FLAT	-	-	FLAT	FLAT	PIN/PEG	-
Terminal pitch	-	2.54 mm	2.54 mm	0.635 mm	-	-	0.635 mm	0.635 mm	2.54 mm	-
Terminal location	-	PERPENDICULAR	PERPENDICULAR	QUAD	-	-	QUAD	QUAD	PERPENDICULAR	-
Maximum time at peak reflow temperature	-	30	30	30	-	-	30	30	30	-
width	-	33.528 mm	33.528 mm	24.1935 mm	-	-	24.1935 mm	24.1935 mm	33.528 mm	-
uPs/uCs/peripheral integrated circuit type	-	DSP PERIPHERAL, FFT PROCESSOR	DSP PERIPHERAL, FFT PROCESSOR	DSP PERIPHERAL, FFT PROCESSOR	-	-	DSP PERIPHERAL, FFT PROCESSOR	DSP PERIPHERAL, FFT PROCESSOR	DSP PERIPHERAL, FFT PROCESSOR	-

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