CD4021BC 8-Stage Static Shift Register
October 1987
Revised March 2002
CD4021BC
8-Stage Static Shift Register
General Description
The CD4021BC is an 8-stage parallel input/serial output
shift register. A parallel/serial control input enables individ-
ual JAM inputs to each of 8 stages. Q outputs are available
from the sixth, seventh, and eighth stages. All outputs have
equal source and sink current capabilities and conform to
standard “B” series output drive.
When the parallel/serial control input is in the logical “0”
state, data is serially shifted into the register synchronously
with the positive transition of the clock. When the parallel/
serial control is in the logical “1” state, data is jammed into
each stage of the register asynchronously with the clock.
All inputs are protected against static discharge with diodes
to V
DD
and V
SS
.
Features
s
Wide supply voltage range:
s
Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
s
5V–10V–15V parametric ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
µ
A at 15V over full tempera-
ture range
3.0V to 15V
s
High noise immunity: 0.45 V
DD
(typ.)
Ordering Code:
Order Number
CD4021BCM
CD4021BCN
Order Code
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Q
n
Parallel/ PI 1 PI n
C
L
Q1
Serial
(Note 2)
(Note 1) Input Serial
(Internal)
Control
X
X
X
X
X
X
X
0
1
X
1
1
1
1
0
0
0
0
0
1
1
X
X
X
0
1
0
1
X
X
X
0
0
1
1
0
1
Q1
0
1
0
1
Q
n−1
Q
n−1
Q
n
X
=
Don't care case
Note 1:
Level change
Note 2:
No change
X
Top View
© 2002 Fairchild Semiconductor Corporation
DS005954
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CD4021BC
Absolute Maximum Ratings
(Note 3)
(Note 4)
Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
(Note 4)
700 mW
500 mW
Recommended Operating
Conditions
(Note 4)
Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
CD4021BCN
3V to 15V
0 to V
DD
−
0.5V to
+
18V
−
0.5V to V
DD
+
0.5V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
Note 3:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Note 4:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
Symbol
I
DD
Parameter
Quiescent Device
Current
V
OL
LOW Level
Output Voltage
V
OH
HIGH Level
Output Voltage
V
IL
LOW Level
Input Voltage
V
IH
HIGH Level
Input Voltage
I
OL
LOW Level Output
Current (Note 5)
I
OH
HIGH Level Output
Current (Note 5)
I
IN
Input Current
Conditions
V
DD
=
5V, V
IN
=
V
DD
or V
SS
V
DD
=
10V, V
IN
=
V
DD
or V
SS
V
DD
=
15V, V
IN
=
V
DD
or V
SS
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
4.6V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
|I
O
|< 1
µA
|I
O
|
<
1
µA
−55°C
Min
Max
5
10
20
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.64
1.6
4.2
−0.64
−1.6
−4.2
−0.1
0.1
3.5
7.0
11.0
0.51
1.3
3.4
−0.51
−1.3
−3.4
4.95
9.95
14.95
Min
+25°C
Typ
0.1
0.2
0.3
0
0
0
5
10
15
2
4
6
3
6
9
0.88
2.2
8
−0.88
−2.2
−8
−10
−
5
10
−
5
−0.1
0.1
1.5
3.0
4.0
Max
5
10
20
0.05
0.05
0.05
+125°C
Min
Max
150
300
600
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.36
0.90
2.4
−0.36
−0.90
−2.4
−1.0
1.0
Units
µA
V
V
V
V
mA
mA
µA
Note 5:
I
OH
and I
OL
are tested one output at a time.
3
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CD4021BC
AC Electrical Characteristics
t
PLH
, t
PHL
Propagation Delay Time
(Note 6)
Min
Typ
240
100
70
100
50
40
2.5
5
8
3.5
10
16
100
50
40
200
100
80
15
15
15
60
40
30
25
15
10
120
80
60
50
30
20
0
10
15
150
75
50
100
50
40
Any Input
5
100
250
125
100
200
100
80
7.5
pF
pF
ns
ns
ns
ns
ns
µs
ns
MHz
Max
350
175
140
200
100
80
ns
ns
Units
T
A
=
25
°
C, input t
r
, t
f
=
20 ns, C
L
=
50 pF, R
L
=
200 kΩ
Symbol
Parameter
Conditions
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
THL
, t
TLH
Transition Time
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
f
CL
Maximum Clock
Input Frequency
t
W
Minimum Clock
Pulse Width
t
r
CL, t
f
CL
Clock Rise and
Fall Time (Note 6)
t
s
Minimum Set-Up Time
Serial Input
t
H
≥
200 ns
(Ref. to CL)
Parallel Inputs
t
H
≥
200 ns
(Ref. to P/S)
t
H
Minimum Hold Time
Parallel/Serial Control
t
WH
Minimum P/S
Pulse Width
t
REM
Minimum P/S Removal
Time (Ref. to CL)
C
I
C
PD
Average Input Capacitance
Power Dissipation
Capacitance (Note 8)
Note 6:
AC Parameters are guaranteed by DC correlated testing.
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Serial In, Parallel In, t
s
≥
400 ns V
DD
=
10V
Note 7:
If more than one unit is cascaded t
r
CL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the esti-
mated capacitive load.
Note 8:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note
AN-90.
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