QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
3.3V CMOS CLOCK
DRIVER/BUFFER
FEATURES:
−
−
−
−
−
−
−
−
JEDEC compatible LVTTL level inputs and outputs
10 output, low skew clock signal buffer
Monitor output
Clock inputs are 5V tolerant
Pinout and function compatible with QS5805T
25Ω on-chip resistors for low noise
Input hysteresis for better noise margin
Guaranteed low skew:
•
0.7ns output skew
•
0.7ns pulse skew
•
1ns part-to-part skew
Std., A, and B speed grades (B speed in QSOP package only)
Available in QSOP and SOIC packages
QS532805/A/B
DESCRIPTION
The QS532805 clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of 5 non-inverting outputs. The QS532805 incorporates 25Ω series
termination resistors. This clock buffer product is designed for use in high
performance workstations, embedded and personal computing systems
using 3V to 3.6V supply voltages. Several can be used in parallel or
scattered throughout a system for guaranteed low skew, system-wide clock
distribution networks. The QS532805 can accept 5V input and control
signals.
The QS532805 is characterized for operation at -40°C to +85°C.
−
−
FUNCTIONAL BLOCK DIAGRAM
OEA
5
INA
OA5
OA1
MON
5
INB
OB5
OB1
OEB
NOTE:
QS532805 has a 25Ω series termination resistor on each clock output, including monitor.
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
JULY 2000
DSC-5785/-
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
V
C CA
OA
1
OA
2
OA
3
G ND
A
OA
4
OA
5
G NDQ
OE
A
IN
A
1
2
3
4
5
6
7
8
9
10
20
19
18
17
SO20-2 16
SO20-8 15
14
13
12
11
V
C CB
OB
1
OB
2
OB
3
G ND
B
OB
4
OB
5
MON
OE
B
IN
B
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM(2)
V
TERM(3)
V
AC
I
OUT
T
STG
T
J
Description
Supply Voltage to Ground
DC Output Voltage V
OUT
DC Input Voltage V
IN
AC Input Voltage (pulse width
≤20ns)
DC Output Current V
IN
< 0
DC Output Current Max. Sink Current/Pin
Storage Temperature
Junction Temperature
(1)
Unit
V
V
V
V
mA
mA
°C
°C
Max.
– 0.5 to +7
– 0.5 to Vcc+0.5
– 0.5 to +7
-3
-20
120
– 65 to +150
150
QSOP/ SOIC
TOP VIEW
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz, V
IN
= 0V, V
OUT
= 0V)
Pins
C
IN
C
OUT
Typ.
4
8
Max.
(1)
6
10
Unit
pF
pF
NOTE:
1. This parameter is guaranteed but not production tested.
RECOMMENDED OPERATING
CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
Description
Power Supply Voltage
Input Voltage
Voltage Applied to Outputs
Ambient Operating Temperature
Min.
3
0
0
– 40
Max
3.6
5.5
V
CC
85
Unit
V
V
V
°C
PIN DESCRIPTION
Pin Names
OEA, OEB
INA, INB
OAn, OBn
MON
I/O
I
I
O
O
Description
Output Enable
Clock Inputs
Clock Outputs
Monitor Outputs (does not 3-state)
2
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
Symbol
V
IH
V
IL
V
IC
V
OH
V
OL
Parameter
Input HIGH Voltage
Input LOW Voltage
Clamp Diode Voltage
(3)
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Guaranteed Logic HIGH for Inputs
Guaranteed Logic LOW for Inputs
Vcc = Min., I
IN
= -18mA
Vcc = Min., I
OH
= -100µA
Vcc = Min., I
OH
= -8mA
Vcc = Min., I
OL
= 100µA
Vcc = Min., I
OL
= 6mA
Vcc = Min., I
OL
= 8mA
I
IN
I
OZ
I
OFF
I
ODH
I
ODL
I
OS
R
OUT
Input Leakage Current
Output Leakage Current
Input Power Off Leakage
Output HIGH Current
(2)
Output LOW Current
(2)
Short Circuit Current
Output Resistance
(2,3)
(4)
Min.
2
–0.5
—
Vcc – 0.2
2.4
—
—
—
—
—
—
–30
30
Typ.
(1)
—
—
–0.7
—
—
—
—
—
—
—
—
–100
100
—
28
Max.
5.5
0.8
–1.2
—
—
0.2
0.4
0.5
±1
±1
±1
–200
200
—
—
Unit
V
V
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
Ω
Vcc = Max., V
IN
= Vcc or GND
Vcc = Max., V
OUT
= Vcc or GND
Vcc = 0V, V
IN
= Vcc or GND
Vcc = 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
Vcc = 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
Vcc = Max., V
OUT
= GND
Vcc = Min
–
60
—
NOTES:
1. Typical values are at V
CC
= 3.3V, T
A
= 25°C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
4. Output resistance represents the total output impedence of the logic device and includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol
I
CC
∆I
CC
I
CCD
I
C
Parameter
Quiescent Power Supply Current
Supply Current per Input HIGH
Dynamic Power Supply Current per Output
(2)
Total Power Supply Current Examples
(2,4)
Test Conditions
(1)
V
CC
= Max., V
IN
= GND or Vcc
V
CC
= Max., V
IN
= Vcc – 0.6V, f = 0MHz
V
CC
= Max.,
OEA
=
OEB
= GND
Outputs Toggling at 50% duty cycle
V
CC
= Max.,
V
IN
= GND or Vcc
OEA
=
OEB
= GND
50% duty cycle, f
I
= 10MHz
V
IN
= GND or 3V
five outputs toggling
V
CC
= Max.,
V
IN
= GND or Vcc
OEA
=
OEB
= GND
50% duty cycle, f
I
= 2.5MHz
V
IN
= GND or 3V
All outputs toggling
Typ.
(3)
0.01
0.1
65
3.3
3.3
1.8
1.8
Max.
100
30
100
5.2
5.2
2.9
2.9
Unit
µA
µA
µA/MHz
mA
mA
mA
mA
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Guaranteed by design but not tested. C
L
= 0pF.
3. Typical values are for reference only. Conditions are V
CC
= 3.3V, T
A
= 25°C.
4. I
C
= I
CC
+ (∆I
CC
)(D
H
)(N
I
) + I
CCD
(f
O
)(N
O
)
where:
D
H
= Input Duty Cycle
N
I
= Number of TTL HIGH inputs at D
H
f
O
= Output Frequency
N
O
= Number of outputs at f
O
3
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SKEW CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
C
LOAD
= 50pF (no resistor)
QS532805
Symbol
t
SK(01)
t
SK(02)
t
SK(P)
t
SK(T)
Parameter
(1)
Skew between all outputs, same transition, same bank
Skew between two outputs, same transition, different banks
Pulse Skew; skew between opposite transitions of the same output (t
PHL
- t
PLH
)
Part-to-part skew
(2)
Min.
—
—
—
—
Max.
0.7
0.9
1
1.5
QS532805A
Min.
—
—
—
—
Max.
0.7
0.9
0.7
1
QS532805B
(3)
Min.
—
—
—
—
Max.
0.7
0.9
0.5
1
Unit
ns
ns
ns
ns
NOTES:
1. This parameter is guaranteed but not production tested. Skew parameters apply to propagation delays only.
2. t
SK(T)
only applies to devices of the same transition, part type, temperature, power supply voltage, loading package, and speed grade.
3. The B speed grade is only available in the QSOP package.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
C
LOAD
= 50pF (no resistor)
QS532805
Symbol
t
PLH
t
PHL
t
R
t
F
t
PZL
t
PZH
t
PLZ
t
PZH
Parameter
(1,2)
Propagation Delay
Output Rise Time, 0.8V to 2V
(3)
Output Fall Time, 2V to 0.8V
(3)
Output Enable Time
Output Disable Time
Min.
1.5
—
—
1.5
1.5
Max.
6.5
2
2
8
7
QS532805A
Min.
1.5
—
—
1.5
1.5
Max.
5.8
2
2
8
7
QS532805B
(4)
Min.
1.5
—
—
1.5
1.5
Max.
5.2
2
2
6.5
6
Unit
ns
ns
ns
ns
ns
NOTES:
1. Minimums guaranteed but not production tested.
2. The propagation delay other range indicated by Min. and Max. specifications results from process and environmental variables. These propagation
delays do not imply limit skew.
3. This parameter is guaranteed but not production tested.
4. The B speed grade is only available in the QSOP package.
4
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
Parameter
Tested
Switch
Position
t
PLZ
, t
PZL
All Others
V
CC
V
IN
Pulse
Generator
50
Ω
DUT
50pF
500
Ω
V
OUT
500
Ω
Closed
Open
6.0 V
Pulse generator for all pulses: f
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
3V
INPUT
t
PLH
t
PHL
V
OH
2.0V
1.5V
0.8V
V
OL
t
R
t
F
t
PLH
OUPUT
t
PHL
V
OH
1.5V
V
OL
t
SK(p)
= t
PHL
- t
PLH
1.5V
0V
INPUT
3V
1.5V
0V
OUPUT
PROPAGATION DELAY
PULSE SKEW — t
SK(P)
3V
3V
INPUT
t
PLHA
V
OH
t
PHLA
V
OH
OUPUT A
1.5V
V
OL
t
SK(02)
OUPUT B
t
SK(02)
V
OH
1.5V
V
OL
t
PLHB
t
PHLB
1.5V
0V
INPUT
t
PLH1
t
PHL1
1.5V
0V
OUPUT 1
1.5V
V
OL
t
SK(01)
t
SK(01)
V
OH
1.5V
V
OL
t
PLH2
t
PHL2
t
SK(01)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
OUPUT 2
t
SK(02)
= t
PLHB
- t
PLHA
or t
PHLB
- t
PHLA
OUTPUT SKEW (SAME BANK) — t
SK(O1)
OUPUT SKEW (DIFFERENT BANKS) — t
SK(O2)
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORM ALLY
LOW
SWITCH
CLOSED
t
PZH
OUTPUT
NORMALLY
HIG H
SWITCH
OPEN
1.5V
DISABLE
3V
1.5V
0V
t
PLZ
3V
1.5V
0.3V V
OL
t
PHZ
0.3V V
OH
PART 2 O UTPUT
t
SK(t)
t
SK(t)
PART 1 O UTPUT
INPUT
t
PLH1
t
PHL1
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
0V
t
PLH2
t
PHL2
3V
1.5V
0V
t
SK(t)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
ENABLE AND DISABLE TIMES
5
PART-TO-PART SKEW — t
SK(T)
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