UNISONIC TECHNOLOGIES CO., LTD
3512
PC POWER SUPPLY
SUPERVISORS
DESCRIPTION
The UTC
3512
is specially designed for switching power supply
system. It provides over-voltage protection, over-current protection,
under-voltage protection, on/off control and power good signal
generating.
OVP/UVP (Over/Under-Voltage Protection) monitors 3.3V, 5V
and double 12V to protect our power supply and PC, FPO goes to
high when one of these supply voltages exceeds their normal
operation voltage range.
OCP (Over Current Protection) monitors IS33, IS5, IS12 input
current. The voltage difference across external current shunt is
used for OCP functions. An external resistor which is connected
between the RI pin and the GND pin can be used to adjust
protection threshold. To achieve better immunity for lighting surge
glitch and to prevent accidental power shut down during dynamic
loading condition, the de-bounce time for UVP/OCP is 73us
respectively. The deglitch time for OVP is 73uS for better noise
immunity.
The power supply is turned on after 38mS de-bounce time when
PSON signal is set from high to low. To turn off power supply,
PSON signal is set from low to high and the de-bounce time is
115mS. When PGI input voltage level is lower than the internal
1.15V reference voltage, after 73uS de-bounce time, the PGO
signal is pulled low.
DIP-14
CMOS IC
SOP-14
*Pb-free plating product number: 3512L
FEATURES
* Over/Under-voltage protection for 3.3V, 5V, and two 12V
* Over-current protection for 3.3V, 5V, and two 12V
* PGO and FPO pins with open drain output stage
* 300mS power good delay from PGI to PGO
* 75mS delay for 3.3V, 5V and 12V power turn on
* 2.8mS delay for PSON control to FPO turn off
* 38mS / 115mS PSON on/off de-bounce time
* 73uS width noise deglitches
* 73uS de-bounce time for UVP and OCP
* Wide supply voltage range
ORDERING INFORMATION
Order Number
Normal
Lead Free Plating
3512-D14-T
3512L-D14-T
3512-S14-R
3512L-S14-R
3512-S14-T
3512L-S14-T
Package
DIP-14
SOP-14
SOP-14
Packing
Tube
Tape Reel
Tube
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Copyright © 2005 Unisonic Technologies Co., Ltd
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QW-R502-073,A
3512
ORDERING INFORMATION(Cont.)
3512L-D14-T
(1)Packing Type
(2)Package Type
(3)Lead Plating
(1) R: Tape Reel, T: Tube
(2) D14: DIP-14, S14: SOP-14
(3) L: Lead Free Plating, Blank: Pb/Sn
CMOS IC
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QW-R502-073,A
3512
PIN CONFIGURATION
CMOS IC
PGI
GND
FPO
PSON
I
S12
RI
V
S12B
1
2
3
4
5
6
7
14
13
12
11
10
9
8
PGO
V
DD
V
S5
V
S33
V
S12
I
S33
I
S5
PIN DESCRIPTION
PIN NO
1
3
4
8
9
PIN NAME
PGI
FPO
PSON
I
S5
I
S33
TYPE
input
output
input
input
input
DESCRIPTION
Power good input.
Fault protection output, open drain output stage.
Power on/off control signal sends from CPU or main-board. The power
supply will be turned on/off after 38mS/115mS respectively.
5V over current protection.
3.3V over current protection.
12V over current protection. Regarding typical application, this pin is
connected to the positive end of a current shunt through one resistor.
When the voltage on IS12 is higher than that of VS12 by 5mV, OCP
will be enabled. One current sink, 8 x I
REF
, is used to determine the
voltage drop between the positive end of the current shunt and VS12.
Adjusting the value of the external resistor can adjust the threshold for
OCP accordingly. The operation for IS5 or IS33 is the same.
Current sense setting. An external resistor Ri is connected between RI
pin and GND pin will adjust a reference current, I
REF
= 1.15/Ri, for OCP
function.
5V over/under-voltage protection.
Second 12V over/under-voltage protection.
12V over/under-voltage protection.
3.3V over/under-voltage protection.
Supply voltage. 4V ~ 15V.
Power good logic output, open drain output stage. The power good
delay is 300mS from PGI to PGO.
Ground.
5
I
S12
input
6
12
7
10
11
13
14
2
RI
V
S5
V
S12B
V
S12
V
S33
V
DD
PGO
GND
input
input
input
input
input
power
output
power
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QW-R502-073,A
3512
BLOCK DIAGRAM
PWR
PSON
38ms /115ms
debounce
RST
V
S33
-
UN
+
-
OV
+
V
S 5
-
UN
+
-
OV
+
V
S12A
-
UN
+
-
OV
+
V
S12 B
-
UN
+
-
OV
+
RST
V
REF
PGI
-
UN
+
V
12A
-
+
I
REF
×8
V
12A
-
+
I
REF
×8
V
12A
I
S12
-
+
V
12A
-
+
I
REF
×8
73µs
debounce
300ms
clr
delay
Power On Reset
2.4 ms
Clr
delay
Clr
75ms
delay
Bandgap
Reference
PWR
CMOS IC
V
REF
=1.15 V
RST
73µs
debounce
R
S Q
FPO
PGO
I
S33
I
S 5
V
REF
=1.15 V
+
-
I
REF
=V
REF
/R
I
R
I
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QW-R502-073,A
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ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
V
DD
V
IN
CMOS IC
RATINGS
UNIT
DC Supply Voltage
-0.3 ~ 16
V
Input Voltage
PSON, V
S33
, V
S5
, PGI
-0.3 ~ 8
V
FPO
-0.3 ~ 16
Output Voltage
V
OUT
V
PGO
-0.3 ~ 8
Power Dissipation
P
D
400
mW
Operating Temperature
T
OPR
-40 ~ +85
℃
Storage Temperature
T
STG
-55 ~ +150
℃
Note 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2.
Stresses above those listed may cause permanent damage to the device.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
DC Supply Voltage
Input Voltage
Input Voltage
Output Voltage
Output Sink Current
PSON, V
S33
, V
S5
, I
S33
, I
S5
, PGI
V
S12
,V
S12B
, I
S12
FPO
PGO
FPO
PGO
See Note
SYMBOL
V
DD
V
IN
V
OUT
I
O(SINK)
t
R
I
RI
1
12.5
MIN
4
MAX
15
7
15
15
7
20
10
62.5
UNIT
V
V
V
mA
mS
µA
Supply Voltage Rising Time
Output Current RI
Note V
DD
rising and falling slew rate must be less than 14V/mS.
ELECTRICAL CHARACTERISTICS
(V
DD
=12V, T
A
=25℃)
PARAMETER
SYMBOL
UNDER-VOLTAGE AND PGI, PGO
Input Threshold Voltage PGI
V
PGI
Under-voltage protect V
S33
V
UVp
Under-voltage protect V
S5
Under-voltage protect V
S12
, V
S12B
Low Level Output Voltage (PGO)
V
OL
Leakage Current (PGO)
I
LEAK
Under-voltage Enable Delay Time
Timing PG Delay
PGI to PGO
t
PG
Noise Deglitch Time
PGI to PGO
Timing UVP to Protection (FPO)
T
UVP
OVER-VOLTAGE AND OVER-CURRENT PROTECTION
Over-Voltage Protection
V
S33
V
OVP
Over-Voltage Protection
V
S5
Over-Voltage Protection
V
S12
, V
S12B
Ratio of Current Sense Sink Current to Current
I
REF
Sense Setting Pin (RI) Source Current
Current Source Reference Voltage
V
REF
OCP Comparator Input Offset Voltage
V
I(OFF)
Low Level Output Voltage (FPO)
V
OL
Leakage Current (FPO)
I
LEAK
Timing OVP to Protection
T
OVP
Timing OCP to Protection
T
OCP
TEST CONDITIONS
MIN
1.1
2.6
4.0
9.4
V
DD
= 12V I
SINK
=10mA
PGO = 5V
49
200
150
V
S33
,V
S5
, V
S12
,V
S12B
3.7
5.7
13.2
RI = 30
ΚΩ,
0.1% Resistor
7.6
1.1
-5
I
SINK
=20mA
V
(FPO)
= 5V
73
73
75
300
250
73
3.9
6.1
13.8
8
1.15
TYP
1.15
2.8
4.2
9.9
MAX
1.2
3.0
4.4
10.4
0.7
5
114
450
350
UNIT
V
V
V
µA
mS
mS
µS
µS
4.1
6.5
14.4
8.4
1.2
5
0.7
5
V
V
mV
V
µA
µS
µS
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