Features
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Full Trusted Computing Group (TCG) Trusted Platform Module (TPM) Version 1.2
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Compatibility
Single-chip Turnkey Solution
Hardware Asymmetric Crypto Engine
2048-bit RSA Sign in 500 ms
AVR
®
RISC Microprocessor
Internal EEPROM Storage for RSA Keys
100 kHz System Management Bus (SMBus
™
) Two-wire Interface
Secure Hardware and Firmware Design and Chip Layout
True Random Number Generator (RNG) - FIPS 140-2 Compliant
NV Storage Space for 1280 bytes of user defined data
3.3V ±10% Supply Voltage
28-lead TSSOP Package or 40-lead QFN Package
0–70°C Temperature Range
Trusted
Platform
Module
AT97SC3203S
SMBus
Two-Wire
Interface
Summary
Description
The AT97SC3203S is a fully integrated security module designed to be integrated into
embedded systems. It implements version 1.2 of the Trusted Computing Group (TCG)
specification for Trusted Platform Modules (TPM).
The TPM includes a cryptographic accelerator capable of computing a 2048-bit RSA
signature in 500 ms and a 1024-bit RSA signature in 100 ms. Performance of the
SHA-1 accelerator is 50 µs per 64-byte block. In most cases, TCG key generation
operations will be completed using a proprietary mechanism in less than 1 msec.
Table 1.
Pin Configurations
Pin Name
V
CC
SB3V
V
BAT
GND
RESET#
SMBDAT
SMBCLK
AVRCLK
Xtall/32K in
XtalO
GPIO6
TestI
TestBI
NC
NBO
Description
3.3V (±10%) Supply Voltage
Standby 3.3V (± 10%) Supply Voltage
2.5–4.0V Battery Input
Ground
Reset Input Active Low
SMBus Data Input/Output
SMBus Clock Input
33-MHz AVR Clock Input
32.768 kHz Crystal Input
32.768 kHz Crystal Output
General Purpose Input/Output
Test Input (disabled)
Test Input (disabled)
No Connect
Not Bonded Out
5132AS–TPM–1/07
Note: This is a summary document. A complete document
is available through your local Atmel sales office.
Figure 1.
Pin Configurations
28-pin TSSOP
6.1 mm x 9.7 mm Body
0.65 mm Pitch
SMBCLK
40-pin QFN
6.0 mm x 6.0 mm Body
0.50 mm Pitch
SMBDAT
NBO
NBO
NBO
NBO
NBO
SMBDAT
SMBCLK
NC
GND
SB3V
GPIO6
NC
TestI
TestBI
V
CC
GND
V
BAT
Xtall/32K in
XtalO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
GND
V
CC
NC
NC
AVRCLK
NC
V
CC
GND
NC
RESET#
NC
NC
GND
SB3V
GPIO6
NC
TestI
TestBI
V
CC
GND
V
BAT
1
2
3
4
5
6
7
8
9
40 39 38 37 36 35 34 33 32 31
NBO
30
29
28
27
26
25
24
23
22
NC
NC
NC
GND
V
CC
NC
NC
AVRCLK
NC
V
CC
GND
NC
10
21
11 12 13 14 15 16 17 18 19 20
XTALO
XTALI/32K in
NBO
NC
Figure 2.
AT97SC3203S Block Diagram
ROM
Program
EEPROM
Program
33 MHz
AVR
Clock Input
SMBDAT
SMBCLK
GPIO6
V
BAT
32.768 kHz
RTC
(Optional)
AVR
8-Bit RISC
CPU
RESET#
NBO
NBO
NBO
NBO
NBO
SRAM
SMBus Interface
GPIO
RNG
EEPROM
Data
CRYPTO
Engine
Timer
Physical
Security
Circuitry
2
AT97SC3203S
5132AS–TPM–1/07
AT97SC3203S
Description (continued)
Communication to and from the TPM occurs through a modified 100-kHz SMBus two-
wire interface. The TPM includes a hardware random number generator, including a
FIPS-approved Pseudo Random Number Generator, that is used for key generation and
TCG protocol functions. The RNG is also available to the system to generate random
numbers that may be needed during normal operation.
The chip uses a dynamic internal memory management scheme to store multiple RSA
keys. Other than the standard TCG commands (TPM_FlushSpecific, TPM_Loadkey2),
no system intervention is required to manage this internal key cache.
Full documentation for TCG primitives can be found on the TCG Web site located at
www.trustedcomputinggroup.org.
This specification includes only mechanical, electrical
and SMBus protocol information
3
5132AS–TPM–1/07
Table 2.
Ordering Information
Ordering Code
AT97SC3203S-X5A40
AT97SC3203S-X5M40
Package
28A3 (28-pin TSSOP)
40ML1 (40-pin QFN)
lead-free, RoHS
lead-free, RoHS
Operation Range
Commercial (0° to 70° C)
Commercial (0° to 70° C)
4
AT97SC3203S
5132AS–TPM–1/07
AT97SC3203S
Package Drawing
28A3 – TSSOP
b
L
L1
E E1
e
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
D
A2
SYMBOL
D
E
E1
MIN
9.60
NOM
9.70
8.10 BSC
MAX
9.80
NOTE
2, 5
6.00
–
0.80
0.19
6.10
–
1.00
–
0.65 BSC
6.20
1.20
1.05
0.30
3, 5
Side View
A
A2
b
e
L
L1
4
0.45
0.60
1.00 REF
0.75
Notes:
1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation DB for additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in)
per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b
dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
1/8/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28A3,
28-lead, 6.1 x 9.7 mm Body, 0.65 pitch,
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
28A3
REV.
A
5
5132AS–TPM–1/07